Abstract: The present disclosure provides a display panel and a display panel manufacturing method. The display panel includes a drive circuit layer, a color photoresist layer disposed on the drive circuit layer, a common electrode layer disposed on the color photoresist layer, and a pixel electrode layer disposed on the common electrode layer. The drive circuit layer is provided with a common wire, the common electrode layer is provided with a transparent electrode, the transparent electrode is electrically connected to the common wire, and the pixel electrode layer is provided with a plurality of pixel electrodes.

Abstract: The present invention provides a full grayscale subjective consistency optical data obtaining method and a splicing display panel, an initial splicing display panel includes splicing and disposing first display panel (liquid crystal display panel) and second display panel in different types. The method includes: obtaining a plurality of bonding point colors, sets of reference bonding point optical parameters and sets of bonding point optical parameters of the first display panel and the second display panel corresponding to the bonding point colors respectively, and determining non-bonding point optical parameters in the second display panel corresponding to non-bonding point colors between adjacent two of the bonding point colors. A display image of the second display panel under effect of each set of the bonding point optical parameters is subjectively consistent with a display image of the first display panel under effect of a set of the reference bonding point optical parameters.

Abstract: A light-emitting panel, a method making same, and a display panel are disclosed in the present disclosure. The light-emitting panel includes a light-emitting board which includes a substrate; a first metal layer disposed on the substrate; a gate insulating layer covering the first metal layer; and a second metal layer on a side of the gate insulating layer away from the first metal layer. The second metal layer includes a connection portion located in the bonding area of the light-emitting board, and a conductive protection layer formed by chemical plating is disposed on a surface of the connection portion.

Abstract: A light-emitting panel, a method making same, and a display panel are disclosed in the present disclosure. The light-emitting panel includes a light-emitting board which includes a substrate; a first metal layer disposed on the substrate; a gate insulating layer covering the first metal layer; and a second metal layer on a side of the gate insulating layer away from the first metal layer. The second metal layer includes a connection portion located in the bonding area of the light-emitting board, and a conductive protection layer formed by chemical plating is disposed on a surface of the connection portion.

Abstract: The manufacturing method for TFT array substrate of the invention exposes the negative photoresist material on the passivation layer with a semi-transmissive mask to form a crosslinked portion, first and second uncrosslinked portion; then, performs the first development to remove the first uncrosslinked portion and forms a via on the passivation layer, performs the ashing treatment for thinning the negative photoresist material to expose the second uncrosslinked portion, performs the second development to remove the second uncrosslinked portion; deposits transparent conductive material on negative photoresist material and exposed passivation layer to form a pixel electrode on passivation layer, and finally removes the remaining negative photoresist material and the transparent conductive material twith photoresist stripping solution.

Abstract: The manufacturing method for TFT array substrate of the invention exposes the negative photoresist material on the passivation layer with a semi-transmissive mask to form a crosslinked portion, first and second uncrosslinked portion; then, performs the first development to remove the first uncrosslinked portion and forms a via on the passivation layer, performs the ashing treatment for thinning the negative photoresist material to expose the second uncrosslinked portion, performs the second development to remove the second uncrosslinked portion; deposits transparent conductive material on negative photoresist material and exposed passivation layer to form a pixel electrode on passivation layer, and finally removes the remaining negative photoresist material and the transparent conductive material with photoresist stripping solution.

Abstract: The present disclosure provides a manufacturing method for an array substrate and a liquid crystal display device. The manufacturing method for an array substrate may include: providing a substrate; forming a thin film transistor device comprising a source and a drain on the substrate; covering a passivation layer, a blocking layer, and a photoresist layer on the thin film transistor device, sequentially; processing the photoresist layer to divide the blocking layer and the passivation layer into a first region and a second region corresponding to positions of an active area, and a third region corresponding to a position of the thin film transistor device. By the above-mentioned manufacturing method, on one hand, a number of mask processes may be reduced, and the manufacturing efficiency may be improved. On the other hand, peeling efficiency of the photoresist may be improved.

Abstract: The present disclosure provides a method for manufacturing a thin-film transistor array substrate including: providing substrate, disposing a gate electrode, a gate insulation layer, and a semiconductor thin film in sequence; depositing a photoresist layer on the semiconductor thin film and pattern the photoresist layer; stripping the photoresist layer to form a source-drain electrode. The present disclosure further provides a thin-film transistor array substrate manufactured by the above method.

Abstract: The present disclosure provides a manufacturing method for an array substrate and a liquid crystal display device. The manufacturing method for an array substrate may include: providing a substrate; forming a thin film transistor device comprising a source and a drain on the substrate; covering a passivation layer, a blocking layer, and a photoresist layer on the thin film transistor device, sequentially; processing the photoresist layer to divide the blocking layer and the passivation layer into a first region and a second region corresponding to positions of an active area, and a third region corresponding to a position of the thin film transistor device. By the above-mentioned manufacturing method, on one hand, a number of mask processes may be reduced, and the manufacturing efficiency may be improved. On the other hand, peeling efficiency of the photoresist may be improved.

Abstract: The present disclosure provides a method for manufacturing an array substrate. An ashing treatment is performed on the first photoresist pattern to remove the photoresist layer in the photoresist-partially-retained-region and to thin the photoresist layer in the photoresist-entirely-retained-region, so that a second photoresist pattern is generated. Thereafter, the passivation layer is etched using the second photoresist pattern as a mask to thin the passivation layer in the photoresist-partially-retained-region and to reduce roughness of the rough top surface in the photoresist-partially-retained-region. Therefore, process stability is raised.

Abstract: The present disclosure provides a method for manufacturing an array substrate. An ashing treatment is performed on the first photoresist pattern to remove the photoresist layer in the photoresist-partially-retained-region and to thin the photoresist layer in the photoresist-entirely-retained-region, so that a second photoresist pattern is generated. Thereafter, the passivation layer is etched using the second photoresist pattern as a mask to thin the passivation layer in the photoresist-partially-retained-region and to reduce roughness of the rough top surface in the photoresist-partially-retained-region. Therefore, process stability is raised.