Abstract: Provided is an array substrate. The array substrate includes at least one pad group disposed in a peripheral region of a base substrate, wherein the at least one pad group includes a sector pad group in which the pads are distributed in a sector shape. Therefore, the bonding yield between the array substrate and the circuit board is increased.

Abstract: An array substrate includes a base substrate, pixel electrodes and common electrodes, first scan lines, second scan lines and data lines. The pixel electrode has first electrode strips disposed at intervals in a row direction. The common electrodes and the pixel electrodes are disposed on the same layer, and the common electrodes have second electrode strips disposed at intervals. The second electrode strips and the first electrode strips are alternatively arranged. The first scan line is located between two adjacent rows of pixel electrodes. The second scan line is located between two adjacent columns of pixel electrodes and is electrically connected to the first scan line, and the second scan line has a scan signal input terminal. The data line has a data signal input terminal. An orthographic projection of the data line on the base substrate intersects with a central region of the pixel electrode on the base substrate.

Abstract: An array substrate includes a base substrate, pixel electrodes and common electrodes, first scan lines, second scan lines and data lines. The pixel electrode has first electrode strips disposed at intervals in a row direction. The common electrodes and the pixel electrodes are disposed on the same layer, and the common electrodes have second electrode strips disposed at intervals. The second electrode strips and the first electrode strips are alternatively arranged. The first scan line is located between two adjacent rows of pixel electrodes. The second scan line is located between two adjacent columns of pixel electrodes and is electrically connected to the first scan line, and the second scan line has a scan signal input terminal. The data line has a data signal input terminal. An orthographic projection of the data line on the base substrate intersects with a central region of the pixel electrode on the base substrate.

Abstract: The present disclosure relates to the field of display technologies and, in particular to a display panel and an electronic device. The display panel comprises: Q rows of first scanning line groups arranged sequentially along a column direction; M columns of second scanning line groups arranged sequentially along a row direction; and at least one gate drive circuit, located on a side of the Q-th row of the first scanning line groups away from the (Q?1)-th row of the first scanning line groups. Each gate drive circuit comprises Q columns of shift register unit groups cascaded in stages. The q-th stage of the shift register unit groups is connected with the q-th row of the first scanning line groups through at least one column of the second scanning line groups. M?Q>1, 1?q?Q, and M, N, Q, q are all positive integers.

Abstract: An array substrate and a display panel are described. The array substrate may include a first base; a plurality of pixel units arrayed on the first base in a row direction and a column direction; each of the pixel units comprising at least two sub-pixels arranged in the row direction; a plurality of first scanning lines sequentially arranged on the first base in the column direction, at least one first scanning line being arranged at a side of each row of pixel units in the column direction, the first scanning lines being connected with the sub-pixels; and a plurality of second scanning lines sequentially arranged on the first base in the row direction, at least one second scanning line being arranged at a side of each column of pixel units in the row direction.

Abstract: Disclose are a display substrate, a liquid crystal display panel and a display device. The display substrate is provided with a display region. The display substrate includes: a base substrate, and a black matrix arranged on a side of the base substrate. The black matrix includes: a first region corresponding to the display region, and a plurality of frame regions arranged on a periphery of the first region. At least one rectilinear first slit and at least one rectilinear second slit intersecting with the at least one rectilinear first slit are arranged in the at least one of the frame regions, and an extending direction of the at least one rectilinear first slit is same as an extending direction of the at least one of the frame regions.

Abstract: A driving method and driving circuit of a display panel, and a display apparatus are disclosed. The driving method includes: at a first display frequency and within a frame of scanning time, loading different first clock signals for 4N number of clock signal lines respectively, and controlling a plurality of shift registers in a gate driving circuit to work in sequence to cause the shift registers output different signals to drive gate lines row by row; and at a second display frequency and within a frame of scanning time, loading the same second clock signal for each clock signal line electrically connected to the same unit group, loading different second clock signals for clock signal lines that are electrically connected to different unit groups, and controlling the unit groups to work in sequence.

Abstract: An Embodiment of the present disclosure provide a display substrate, including a base substrate, and a plurality of first scanning lines, a plurality of second scanning lines, a plurality of data lines, a plurality of common electrodes and a plurality of pixel electrodes on the base substrate. The second scanning lines are parallel to the data lines, and the second scanning lines, the common electrodes and the pixel electrodes are in different layers. The common electrodes are located on a side of the second scanning lines and the data lines away from the base substrate, and on a side of the pixel electrodes proximal to the base substrate. An orthographic projection of one of the data line and the second scanning line on the base substrate is located in a spacer region between adjacent pixel electrodes.

Abstract: A mask is provided in embodiments of the disclosure, at least including: a first light transmission area provided with a first optical filter film; and a second light transmission area provided with a second optical filter film; the first optical filter film and the second optical filter film comprise respective materials through which light of different frequency ranges is optically filtered, respectively. A method for manufacturing a mask, a lithography method, a display panel, a display device, and an exposure device are further provided in embodiments of the disclosure.

Abstract: An array substrate includes a base substrate, pixel electrodes and common electrodes, first scan lines, second scan lines and data lines. The pixel electrode has first electrode strips disposed at intervals in a row direction. The common electrodes and the pixel electrodes are disposed on the same layer, and the common electrodes have second electrode strips disposed at intervals. The second electrode strips and the first electrode strips are alternatively arranged. The first scan line is located between two adjacent rows of pixel electrodes. The second scan line is located between two adjacent columns of pixel electrodes and is electrically connected to the first scan line, and the second scan line has a scan signal input terminal. The data line has a data signal input terminal. An orthographic projection of the data line on the base substrate intersects with a central region of the pixel electrode on the base substrate.

Abstract: Provided is an array substrate. The array substrate includes at least one pad group disposed in a peripheral region of a base substrate, wherein the at least one pad group includes a sector pad group in which the pads are distributed in a sector shape. Therefore, the bonding yield between the array substrate and the circuit board is increased.

Abstract: Disclose are a display substrate, a liquid crystal display panel and a display device. The display substrate is provided with a display region. The display substrate includes: a base substrate, and a black matrix arranged on a side of the base substrate. The black matrix includes: a first region corresponding to the display region, and a plurality of frame regions arranged on a periphery of the first region. At least one rectilinear first slit and at least one rectilinear second slit intersecting with the at least one rectilinear first slit are arranged in the at least one of the frame regions, and an extending direction of the at least one rectilinear first slit is same as an extending direction of the at least one of the frame regions.

Abstract: Disclosed are a shift register unit, a gate drive circuit and a display device. The shift register unit includes: the input circuit provides the signal of the input signal end to the first node; the reset circuit provides the signal of the first reference signal end to the first node in response to the signal of the reset signal end; the control circuit controls the signals of the first node and the second node, and the output circuit provides the signal of the clock signal end to the drive output end in response to the signal of the first node, and provides the signal of the second reference signal end to the drive output end in response to the signal of the second node; the signal of the first reference signal end and the signal of the second reference signal end are loaded independently of each other.

Abstract: A mask is provided in embodiments of the disclosure, at least including: a first light transmission area provided with a first optical filter film; and a second light transmission area provided with a second optical filter film; the first optical filter film and the second optical filter film comprise respective materials through which light of different frequency ranges is optically filtered, respectively. A method for manufacturing a mask, a lithography method, a display panel, a display device, and an exposure device are further provided in embodiments of the disclosure.

Abstract: The present disclosure provides a pixel driving circuit, a driving method, a pixel unit, and a display apparatus. The pixel driving circuit includes a driving transistor, a charging/discharging circuitry, a light-emitting control circuitry, a data write-in control circuitry, and a charging/discharging control circuitry, where a first electrode of the charging/discharging circuitry is connected to a second electrode of the driving transistor, and the charging/discharging control circuitry is configured to enable a first electrode of the driving transistor to be electrically connected to a second level output terminal under the control of a data line, and enable a second terminal of the charging/discharging circuitry to be electrically connected to a gate electrode of the driving transistor under the control of a first scan line.

Abstract: A shift register, a gate driver, a display panel and a driving method are provided. The shift register includes an input-reset circuit, which is connected with a pull-up node; and a driving circuit, which is connected with the pull-up node. The input-reset circuit is configured to: write a voltage of a first signal into the pull-up node in response to a second signal, in an input phase of forward scanning; write a voltage of a fourth signal into the pull-up node in response to a third signal, in a reset phase of forward scanning; write the voltage of the fourth signal into the pull-up node in response to the third signal, in an input phase of reverse scanning; and write the voltage of the first signal into the pull-up node in response to the second signal, in a reset phase of reverse scanning.

Abstract: An array substrate and a manufacturing method thereof, and a display device are provided. The array substrate includes a plurality of mutually parallel signal lines, an insulating layer located on a layer in which the plurality of signal lines is located and at least one first conductive structure located on the insulating layer. The insulating layer includes at least two first through holes corresponding to the first conductive structure, and the first conductive structure is electrically connected with the signal lines through the at least two first through holes.

Abstract: A shift register, a gate driver, a display panel and a driving method are provided. The shift register includes an input-reset circuit, which is connected with a pull-up node; and a driving circuit, which is connected with the pull-up node. The input-reset circuit is configured to: write a voltage of a first signal into the pull-up node in response to a second signal, in an input phase of forward scanning; write a voltage of a fourth signal into the pull-up node in response to a third signal, in a reset phase of forward scanning; write the voltage of the fourth signal into the pull-up node in response to the third signal, in an input phase of reverse scanning; and write the voltage of the first signal into the pull-up node in response to the second signal, in a reset phase of reverse scanning.

Abstract: A pixel circuit is disclosed, which includes a charging module, a storage module, an adjusting module, a data-in module, a drive module, and a light-emitting device. A first end of the charging module is configured to receive a first voltage signal, a second end of the charging module is coupled to a first end of the light-emitting device, and a third end of the charging module is coupled to a first end of the memory module, a second end of the light-emitting device and a first end of the drive module. A second end of the storage module is coupled to a first end of the adjusting module. A second end of the adjusting module is coupled to a second end of the data-in module and a third end of the drive module. A first end of the data-in module is configured to receive a data signal.

Abstract: A pixel circuit is disclosed, which includes a charging module, a storage module, an adjusting module, a data-in module, a drive module, and a light-emitting device. A first end of the charging module is configured to receive a first voltage signal, a second end of the charging module is coupled to a first end of the light-emitting device, and a third end of the charging module is coupled to a first end of the memory module, a second end of the light-emitting device and a first end of the drive module. A second end of the storage module is coupled to a first end of the adjusting module. A second end of the adjusting module is coupled to a second end of the data-in module and a third end of the drive module. A first end of the data-in module is configured to receive a data signal.