Patents by Inventor Marc A. Auslander
Marc A. Auslander has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7526609Abstract: Methods and arrangements for accessing a storage structure. Included are an arrangement for providing a storage access instruction, an arrangement for inputting an address into a storage structure data cache responsive to a storage access instruction, an arrangement for extending a storage access instruction with a predicted register number field, the predicted register number field containing a predicted register number corresponding to a speculative location of a load/store operand associated with a storage access instruction, an arrangement for speculatively accessing a storage structure with a storage access instruction extended by the extending arrangement, and an arrangement for reverting to the arrangement for inputting an address if the load/store operand is not in the speculative location.Type: GrantFiled: October 26, 2007Date of Patent: April 28, 2009Assignee: International Business Machines CorporationInventors: Kartik Agaram, Marc A. Auslander, Kemal Ebcioglu
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Patent number: 7516276Abstract: Methods and arrangements for accessing a storage structure. Included are an arrangement for providing a storage access instruction, an arrangement for inputting an address into a storage structure data cache responsive to a storage access instruction, an arrangement for extending a storage access instruction with a predicted register number field, the predicted register number field containing a predicted register number corresponding to a speculative location of a load/store operand associated with a storage access instruction, an arrangement for speculatively accessing a storage structure with a storage access instruction extended by the extending arrangement, and an arrangement for reverting to the arrangement for inputting an address if the load/store operand is not in the speculative location.Type: GrantFiled: October 30, 2007Date of Patent: April 7, 2009Assignee: International Business Machines CorporationInventors: Kartik Agaram, Marc A. Auslander, Kemal Ebcioglu
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Publication number: 20080052470Abstract: Methods and arrangements for accessing a storage structure. Included are an arrangement for providing a storage access instruction, an arrangement for inputting an address into a storage structure data cache responsive to a storage access instruction, an arrangement for extending a storage access instruction with a predicted register number field, the predicted register number field containing a predicted register number corresponding to a speculative location of a load/store operand associated with a storage access instruction, an arrangement for speculatively accessing a storage structure with a storage access instruction extended by the extending arrangement, and an arrangement for reverting to the arrangement for inputting an address if the load/store operand is not in the speculative location.Type: ApplicationFiled: October 30, 2007Publication date: February 28, 2008Applicant: International Business Machines CorporationInventors: Kartik Agaram, Marc Auslander, Kemal Ebcioglu
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Publication number: 20080046654Abstract: Methods and arrangements for accessing a storage structure. Included are an arrangement for providing a storage access instruction, an arrangement for inputting an address into a storage structure data cache responsive to a storage access instruction, an arrangement for extending a storage access instruction with a predicted register number field, the predicted register number field containing a predicted register number corresponding to a speculative location of a load/store operand associated with a storage access instruction, an arrangement for speculatively accessing a storage structure with a storage access instruction extended by the extending arrangement, and an arrangement for reverting to the arrangement for inputting an address if the load/store operand is not in the speculative location.Type: ApplicationFiled: October 26, 2007Publication date: February 21, 2008Applicant: International Business Machines CorporationInventors: Kartik Agaram, Marc Auslander, Kemal Ebcioglu
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Patent number: 7290092Abstract: Methods and arrangements for accessing a storage structure. Included are an arrangement for providing a storage access instruction, an arrangement for inputting an address into a storage structure data cache responsive to a storage access instruction, an arrangement for extending a storage access instruction with a predicted register number field, the predicted register number field containing a predicted register number corresponding to a speculative location of a load/store operand associated with a storage access instruction, an arrangement for speculatively accessing a storage structure with a storage access instruction extended by the extending arrangement, and an arrangement for reverting to the arrangement for inputting an address if the load/store operand is not in the speculative location.Type: GrantFiled: December 10, 2003Date of Patent: October 30, 2007Assignee: International Business Machines CorporationInventors: Kartik Agaram, Marc A. Auslander, Kemal Ebcioglu
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Publication number: 20050251806Abstract: A system, method and computer program product for enhancing a real-time operating system (RTOS) with functionality normally associated with a general purpose operating system (GPOS). A hypervisor that is adapted to perform a real-time scheduling function supports concurrent execution of an RTOS and a GPOS on a system of shared hardware resources. The RTOS or its applications can utilize services provided by the GPOS. Such services may include one or more of file system organization, network communication, network management, database management, security, user-interface support and others. To enhance operational robustness and security, the hypervisor can be placed in read-only storage while maintaining the ability to update scheduling mechanisms. A programmable policy manager that is maintained in read-write storage can be used to dictate scheduling policy changes to the hypervisor as required to accommodate current needs.Type: ApplicationFiled: May 10, 2004Publication date: November 10, 2005Inventors: Marc Auslander, Boas Betzler, Dilma Da Silva, Michael Day, Orran Krieger, Paul McKenney, Michal Ostrowski, Bryan Rosenburg, Robert Wisniewski, James Xenidis
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Publication number: 20050132139Abstract: Methods and arrangements for accessing a storage structure. Included are an arrangement for providing a storage access instruction, an arrangement for inputting an address into a storage structure data cache responsive to a storage access instruction, an arrangement for extending a storage access instruction with a predicted register number field, the predicted register number field containing a predicted register number corresponding to a speculative location of a load/store operand associated with a storage access instruction, an arrangement for speculatively accessing a storage structure with a storage access instruction extended by the extending arrangement, and an arrangement for reverting to the arrangement for inputting an address if the load/store operand is not in the speculative location.Type: ApplicationFiled: December 10, 2003Publication date: June 16, 2005Applicant: IBM CorporationInventors: Kartik Agaram, Marc Auslander, Kemal Ebcioglu
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Publication number: 20050071811Abstract: Systems, especially operating systems, are becoming more complex to the point where maintaining them by humans is becoming nearly impossible. Many corporations have recognized this trend and have begun investing in autonomic technology. Autonomic technology allows a piece of software to monitor, diagnose, and repair itself. This can be used for improved performance, reliability, maintainability, security, etc. Disclosed herein is a mechanism to allow operating systems to hot swap a piece of operating system code, while continuing to offer to the user the service which that code is providing. This can be used, for examples, to increase the performance of an application or to fix a detected security hole live without bringing the machine down. Some autonomic ability will be mandatory in next generation operating system for without it they will collapse under their own complexity. The invention offers a key component of being able to achieve autonomic computing.Type: ApplicationFiled: September 29, 2003Publication date: March 31, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jonathan Appavoo, Marc Auslander, Kevin Hui, Orran Krieger, Dilma Silva, Robert Wisniewski
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Publication number: 20030200457Abstract: A method for allowing a system programmer using a computing system to efficiently use a queuing lock without the requirement of pre-allocating qnode structures for each possible thread of computation expecting to use the lock. More specifically, the lock structure of this invention uses two pointers: a head pointer that points to the next qnode structure representing the next thread or process interested in acquiring the lock, and a tail pointer pointing to the qnode structure representing the last thread or process in a queue of threads or processes awaiting to acquire the lock. When the lock is released, a flag is changed in the qnode structure of the next thread in line (pointed to by the head of the lock) indicating that thread now has the lock and may proceed. A thread or process obtains the lock by spinning on a flag in a qnode structure representing such thread or process.Type: ApplicationFiled: April 23, 2002Publication date: October 23, 2003Applicant: International Business Machines CorporationInventors: Marc A. Auslander, David Joel Edelsohn, Orran Yaakov Krieger, Bryan Savoye Rosenburg, Robert W. Wisniewski
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Patent number: 5129088Abstract: A data processing method for storing groups of related information in a storage subsystem of a data processing system in which the storage subsystem includes one or more storage devices having a plurality of block addressable storage locations (blocks or sectors) each of which stores a predetermined fixed number of bytes of said information. The method includes the step of establishing allocatable increments of storage, called physical partitions, which comprise a predetermined number of contiguous addressable blocks, and initially allocating, in response to a request to the operating system, a preselected number of partitions for each group of related information, where the partitions in each group are not necessarily physically contiguous and where the number that is selected is the minimum number of partitions required to store the group of related information.Type: GrantFiled: July 3, 1990Date of Patent: July 7, 1992Assignee: International Business Machines CorporationInventors: Marc A. Auslander, Albert Chang, Stephen P. Morgan, John T. O'Quin, II, John C. O'Quin, III
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Patent number: 4656583Abstract: A method for use during the optimizatin phase of an optimizing compiler for performing global common subexpression elimination and code motion which comprises:Determining the code `basis` for the object program which includes examining each basic block of code and determining the `basis` items on which each computation depends wherein `basis` items are defined as operands which are referenced in a basic block before being computed. The method next determines the "kill set" for each `basis` item. Following this UEX, DEX, and THRU are determined for each basic block using the previously determined `basis` and "kill set" information. AVAIL and INSERT are computed from UEX, DEX, and THRU, and appropriate code insertions are made at those locations indicated by the preceding step, and finally redundant code is removed using the AVAIL set.Type: GrantFiled: August 13, 1984Date of Patent: April 7, 1987Assignee: International Business Machines CorporationInventors: Marc A. Auslander, John Cocke, Peter W. Markstein
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Patent number: 4642764Abstract: A method operable within an optimizing compiler for generating Basis items and Kill Sets for use during subsequent global common subexpressions elimination and code motion procedures. More particularly, the method comprises assigning a symbolic register to each non-basis element to be computed as follows: creating a tuple (v) for each computation which is to be converted to a machine instruction by the compiler creating a table (optimally, a hash table) having an entry for all the tuples in the program being compiled; for every Basis element in a tuple being entered in the table a symbolic register uniquely assigned to that tuple is added to the Kill Set for that Basis element. For every non-basis element "n" in the tuple being entered into the table, the uniquely assigned symbolic register for that tuple is added to the Kill Sets for all the Basis elements in whose Kill Sets that non-basis element "n" appears.Type: GrantFiled: August 13, 1984Date of Patent: February 10, 1987Assignee: International Business Machines CorporationInventors: Marc A. Auslander, Martin E. Hopkins, Peter W. Markstein
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Patent number: 4589087Abstract: A mechanism including an expanded condition register for use in a reduced instruction set computing system which facilitates the performance of single machine cycle instructions on the system and further provides for the efficient execution of more complex instructions which are not susceptible of being completed in a single machine cycle. More particularly, a mechanism is provided for setting the bits of the expanded condition register whereby a more efficient restart is possible after a machine interrupt and whereby the results of intermediate operations of certain multistep logic and arithmetic operations are maintained in the condition register in order that the cycle time of such multistep operations may be kept to a minimum, and when necessary, may be executed with greater efficiency.Type: GrantFiled: June 30, 1983Date of Patent: May 13, 1986Assignee: International Business Machines CorporationInventors: Marc A. Auslander, John Cocke, Hsieh T. Hao, Peter W. Markstein, George Radin
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Patent number: 4589065Abstract: A mechanism for performing a run-time storage address validity check within one machine cycle. The mechanism, functioning together with an intelligent compiler, eliminates the need for hardware implementation of a storage validity check. More particularly, the mechanism performs its function in one machine cycle in the event that a trap exception does not cause an interrupt. In the rare instance when an interrupt is necessary, a number of machine cycles will be impacted. The mechanism comprises a minimum amount of logic circuitry for determining the trap condition operating in conjunction with conventional, previously existing compare, branch instruction testing, and interrupt generation circuitry.Type: GrantFiled: June 30, 1983Date of Patent: May 13, 1986Assignee: International Business Machines CorporationInventors: Marc A. Auslander, John Cocke, Hsieh T. Hao, Peter W. Markstein, George Radin