Abstract: Apparatus, systems, and/or methods may include a peripheral component interconnect express (PCIe) link to directly couple a slot with a network fabric. The slot may be defined by a surface and/or may accommodate a hardware module. A rack unit implementation may be utilized, such as a one rack unit (1U) implementation, a four rack unit (4U) implementation, and so on. The network fabric may be utilized when hardware modules communicate across the PCIe link, may be bypassed when hardware modules communicate across an additional PCIe link, and so on. The PCIe link may include a direct connect point-to-point PCIe link, a dual star PCIe link, and so on. In addition, the PCIe link may be utilized in a rack-scale architecture.

Abstract: Apparatus, systems, and/or methods may include a peripheral component interconnect express (PCIe) link to directly couple a slot with a network fabric. The slot may be defined by a surface and/or may accommodate a hardware module. A rack unit implementation may be utilized, such as a one rack unit (1U) implementation, a four rack unit (4U) implementation, and so on. The network fabric may be utilized when hardware modules communicate across the PCIe link, may be bypassed when hardware modules communicate across an additional PCIe link, and so on. The PCIe link may include a direct connect point-to-point PCIe link, a dual star PCIe link, and so on. In addition, the PCIe link may be utilized in a rack-scale architecture.

Abstract: Apparatus, systems, and/or methods may include a peripheral component interconnect express (PCIe) link to directly couple a slot with a network fabric. The slot may be defined by a surface and/or may accommodate a hardware module. A rack unit implementation may be utilized, such as a one rack unit (1 U) implementation, a four rack unit (4 U) implementation, and so on. The network fabric may be utilized when hardware modules communicate across the PCIe link, may be bypassed when hardware modules communicate across an additional PCIe link, and so on. The PCIe link may include a direct connect point-to-point PCIe link, a dual star PCIe link, and so on. In addition, the PCIe link may be utilized in a rack-scale architecture.

Abstract: A transaction processing method is disclosed to solve the issue of multiple producers (software and hardware) and one or more consumers operating in a peer or hierarchical system. The transaction processing method is a deterministic method operable in a system having any number of producers. The producers themselves may be any combination of hardware and software and may be part of peer or hierarchical systems.

Abstract: Apparatus, systems, and/or methods may include a peripheral component interconnect express (PCIe) link to directly couple a slot with a network fabric. The slot may be defined by a surface and/or may accommodate a hardware module. A rack unit implementation may be utilized, such as a one rack unit (1 U) implementation, a four rack unit (4 U) implementation, and so on. The network fabric may be utilized when hardware modules communicate across the PCIe link, may be bypassed when hardware modules communicate across an additional PCIe link, and so on. The PCIe link may include a direct connect point-to-point PCIe link, a dual star PCIe link, and so on. In addition, the PCIe link may be utilized in a rack-scale architecture.

Abstract: A transaction processing method is disclosed to solve the issue of multiple producers (software and hardware) and one or more consumers operating in a peer or hierarchical system. The transaction processing method is a deterministic method operable in a system having any number of producers. The producers themselves may be any combination of hardware and software and may be part of peer or hierarchical systems.

Abstract: A method and apparatus to enable data integrity checking of a block of data while the block of data is being transferred from a volatile memory to a non-volatile storage device is provided. The data integrity checking is performed in conjunction with Direct Memory Access operations and Redundant Array of Independent Disk (RAID) operations. In addition, data integrity checking of syndrome blocks in the RAID is performed during transfers to/from the storage devices in the RAID system and during RAID update and RAID data reconstruction operations.

Abstract: A method and apparatus to enable data integrity checking of a block of data while the block of data is being transferred from a volatile memory to a non-volatile storage device is provided. The data integrity checking is performed in conjunction with Direct Memory Access operations and Redundant Array of Independent Disk (RAID) operations. In addition, data integrity checking of syndrome blocks in the RAID is performed during transfers to/from the storage devices in the RAID system and during RAID update and RAID data reconstruction operations.

Abstract: Provided are a method, system, and article of manufacture for providing data integrity for data streams. Input data streams are received. A parity data stream is generated by computing parity data from the input data streams, wherein the parity data stream comprises data blocks. Data integrity fields are computed for the data blocks, wherein a data integrity field is used to ensure the integrity of a data block for which the data integrity field is computed. The computed data integrity fields are added to the data blocks to generate an output stream.

Abstract: Described are a system and method of accessing vital product data (VPD) information. A first processing system may initiate a configuration write request to a VPD address register. A second processing system may access a VPD data register associated with the VPD address register in response to an interrupt signal.

Abstract: Disclosed are a system and method of replacing data in cache ways of a cache memory array. If one or more cache ways are locked from replacement, a cache way may be selected from among the unlocked cache ways based upon a pseudo random selection scheme.

Abstract: Embodiments of the present invention provide for configurable memory bus width and memory reclamation. In particular, the memory controller is configured to use a width of memory that is less than that fully available such that back-to-back writes can occur, as opposed to read-modify-writes. Unused regions of memory (defined by the total available memory width subtracted by the managed memory width) are partially or fully reclaimed, thus increasing the effective memory size available to the user. The configuration methods accommodate multiple interface bus widths while maintaining bandwidth not previously possible.

Abstract: A method and apparatus for providing a configurable memory data width including a device supporting a first data width, a memory supporting a second data width, and a controller. The controller configures a first sub-region of memory having a data width less than that fully available when the data width supported by the device differs from the data width supported by the region of memory, and maps data from the device to the configured first sub-region of the memory. The controller implements a constant in an unused region of the memory, and calculates error correction data based upon the data mapped in the sub-region of the memory and the constant value in the unused region of the memory.

Abstract: Disclosed are a system and method of configuring a device or device function to claim bus transactions. A host processing system may execute an enumeration procedure to configure one or more devices coupled to a data bus. At least one of a device and a device function may be concealed from the host processing system during the enumeration procedure. The concealed device or device function may be configured to claim bus transaction requests initiated by an entity independently of the host processing system.

Abstract: Described are a system and method of accessing vital product data (VPD) information. A first processing system may initiate a configuration write request to a VPD address register. A second processing system may access a VPD data register associated with the VPD address register in response to an interrupt signal.

Abstract: An interrupt controller may receive a plurality of interrupts from a variety of sources. An interrupt source register may be utilized to determine the interrupt source. A prioritizer may then determine the priority of each interrupt based on the source of the interrupt. The prioritizer then controls which interrupts are forwarded to a vector generator. The vector generator calculates a interrupt service routine vector of the highest priority interrupt for the core processor. As a result, the core processor receives only the highest priority interrupt vector. When the core processor has finished processing the highest priority interrupt, in some embodiments, the next highest priority interrupt vector is then forwarded for handling.

Abstract: Disclosed are a system and method of replacing data in cache ways of a cache memory array. If one or more cache ways are locked from replacement, a cache way may be selected from among the unlocked cache ways based upon a pseudo random selection scheme.

Abstract: A computer system is provided including a local memory, a local bus coupled to the local memory, a peripheral bus and a direct memory access (DMA) controller. The DMA controller performs DMA transfers of data between the local bus and the peripheral bus. The DMA includes a DMA queue for storing data to be transferred and a bus ownership status circuit for determining bus ownership status of the DMA controller. The DMA controller further includes a local bus interface circuit coupled to the DMA queue and to the status circuit for halting the transfer of data from the local bus to the DMA queue without relinquishing DMA ownership over the local bus when the DMA queue is full and the status circuit indicates that the DMA controller has ownership over both the peripheral bus and the local bus.