Abstract: A system architecture including a co-processor and a memory switch resource is disclosed. The memory switch includes multiple memory blocks and switch circuitry for selectably coupling processing units of the co-processor, and also a bus slave circuit coupled to a system bus of the system, to selected ones of the memory blocks. The memory switch may be constructed as an array of multiplexers, controlled by control logic of the memory switch in response to the contents of a control register. The various processing units of the co-processor are each able to directly access one of the memory blocks, as controlled by the switch circuitry. Following processing of a block of data by one of the processing units, the memory switch associates the memory blocks with other functional units, thus moving data from one functional unit to another without requiring reading and rewriting of the data.

Abstract: A master and a slave stage of a flip-flop are each separately clocked with non-overlapping clock signals during scan mode to eliminate a data input scan mode multiplexer. Separate, non-overlapping clocking permits the elimination of hold violations in scan mode for scan mode flip flop chains, permitting the elimination of delay buffers in the scan mode data paths. Resulting application circuits have reduced circuit area, power consumption and noise generation. A clock generator for scan mode clocking is provided to obtain the separate, non-overlapping scan mode clocks. Scan mode clocks may be generated with a toggle flip flop, a pulse generator or a clock gating circuit.

Abstract: The method of the present disclosure permits the synthesis of any virtual cell by means of an abstraction, including that of an enable flop, full adder, half adder, or multi-stage multiplexer, based on the ability to extract timing information and add a timing margin to account for clock latency. Specifically, the method of the present disclosure takes advantage of the ability to create synthesis abstractions to build a model of a clock gated enable flop. The synthesis abstraction operates on the assumption that every enable flop has an internally gated clock. The synthesis abstraction may be constructed according to various scripts or algorithms.

Abstract: The system and method disclosed here are directed to desensitization of paths to perturbations resulting from manufacturing faults. A threshold value for signal slew filters out some near-critical paths, and a mathematical formula is applied to determine the appropriate upsize for the cell driving the net along the near-critical path. The cell driving the net may be then be upsized in order to improve the timing through the cell, increase the positive slack, and reduce the sensitivity of the net to design perturbations.

Abstract: A system and method for repairing crosstalk delays are disclosed herein. By modeling the change in effective capacitance, one may determine the delay attributable to crosstalk, and upsize cells in the failing net according to a mathematical formula in order to counter the delay.

Abstract: An exercise assembly includes a hollow, substantially rectangular housing having a pair of side walls, a rear wall, an openable front wall and an open top in communication with an interior chamber. A cord encompasses a pulley system inside the interior chamber and exits the housing at its open top. The side and rear walls each have a pair of aligned rows of apertures for receiving an anchoring assembly. The anchoring assembly includes two outwardly extending legs which may be placed beneath a furniture item to stabilize the device while a user performs a desired exercise.