Abstract: Emulating a circuit design includes receiving a circuit design. The circuit design is mapped onto integrated circuit (IC) devices. Further, the circuit design that is mapped onto the IC devices is instrumented by inserting a first change detection circuit and a first synchronization circuit. The first synchronization circuit is connected to the first change detection circuit and stops emulation on one of the IC devices based on an output of the first change detection circuit and completion of a first one or more emulation cycles. Further, the IC devices are provided for emulation.

Abstract: A computer-implemented method generates a plurality of clusters based on components included in a design under test (DUT); classifies a subset of clusters of the plurality of clusters as tangled clusters; modifies at least two tangled clusters of the subset of clusters based on overlap between the at least two tangled clusters; determines, for each tangled cluster in the subset of clusters, a gate count based on the interconnectivity of the tangled cluster; and partitions the DUT among a plurality of field-programmable gate arrays (FPGAs) based on the gate count determined for each tangled cluster from the subset of clusters.

Abstract: A computer-implemented method generates a plurality of clusters based on components included in a design under test (DUT); classifies a subset of clusters of the plurality of clusters as tangled clusters; modifies at least two tangled clusters of the subset of clusters based on overlap between the at least two tangled clusters; determines, for each tangled cluster in the subset of clusters, a gate count based on the interconnectivity of the tangled cluster; and partitions the DUT among a plurality of field-programmable gate arrays (FPGAs) based on the gate count determined for each tangled cluster from the subset of clusters.