Abstract: A memory device includes a string of series-connected memory cells, a data line, a first select transistor, a common source, a second select transistor, and a gate leakage transistor. The string of series-connected memory cells includes a vertical channel region. Each memory cell of the string of series-connected memory cells includes a first gate stack structure. The data line is connected to the vertical channel region. The first select transistor is connected between the data line and the string of series-connected memory cells. The second select transistor is connected between the common source and the string of series-connected memory cells. The gate leakage transistor is connected between the first select transistor and the second select transistor. The gate leakage transistor includes a second gate stack structure different from the first gate stack structure.

Abstract: A memory device includes a string of series-connected memory cells, a data line, a first select transistor, a common source, a second select transistor, and a gate leakage transistor. The string of series-connected memory cells includes a vertical channel region. Each memory cell of the string of series-connected memory cells includes a first gate stack structure. The data line is connected to the vertical channel region. The first select transistor is connected between the data line and the string of series-connected memory cells. The second select transistor is connected between the common source and the string of series-connected memory cells. The gate leakage transistor is connected between the first select transistor and the second select transistor. The gate leakage transistor includes a second gate stack structure different from the first gate stack structure.

Abstract: An apparatus comprises a stack comprising an alternating sequence of dielectric structures and conductive structures, a first channel material extending vertically through the stack, and a second channel material adjacent the first channel material and extending vertically through the stack. The first channel material has a first band gap and the second channel material has a second band gap that is relatively larger than the first band gap. The apparatus further comprises a conductive plug structure adjacent to each of the first channel material and the second channel material, and a conductive line structure adjacent to the conductive plug structure. Methods of forming the apparatus, memory devices, and electronic systems are also described.

Abstract: An apparatus comprises a stack comprising an alternating sequence of dielectric structures and conductive structures, a first channel material extending vertically through the stack, and a second channel material adjacent the first channel material and extending vertically through the stack. The first channel material has a first band gap and the second channel material has a second band gap that is relatively larger than the first band gap. The apparatus further comprises a conductive plug structure adjacent to each of the first channel material and the second channel material, and a conductive line structure adjacent to the conductive plug structure. Methods of forming the apparatus, memory devices, and electronic systems are also described.

Abstract: Back gates and related apparatuses, systems, and methods are disclosed. An apparatus includes a channel material including a first side and a second side opposite the first side. The apparatus also includes word lines comprising electrically conductive material spaced along the first side of the channel material. The apparatus further includes a back gate comprising electrically conductive material proximate to the second side of the channel material. A method includes biasing a bit line and a word line associated with a memory cell according to a memory operation, and biasing the back gate while biasing the bit line and the word line.

Abstract: Back gates and related apparatuses, systems, and methods are disclosed. An apparatus includes a channel material including a first side and a second side opposite the first side. The apparatus also includes word lines comprising electrically conductive material spaced along the first side of the channel material. The apparatus further includes a back gate comprising electrically conductive material proximate to the second side of the channel material. A method includes biasing a bit line and a word line associated with a memory cell according to a memory operation, and biasing the back gate while biasing the bit line and the word line.

Abstract: Back gates and related apparatuses, systems, and methods are disclosed. An apparatus includes a channel material including a first side and a second side opposite the first side. The apparatus also includes word lines comprising electrically conductive material spaced along the first side of the channel material. The apparatus further includes a back gate comprising electrically conductive material proximate to the second side of the channel material. A method includes biasing a bit line and a word line associated with a memory cell according to a memory operation, and biasing the back gate while biasing the bit line and the word line.

Abstract: An apparatus comprises a stack comprising an alternating sequence of dielectric structures and conductive structures, a first channel material extending vertically through the stack, and a second channel material adjacent the first channel material and extending vertically through the stack. The first channel material has a first band gap and the second channel material has a second band gap that is relatively larger than the first band gap. The apparatus further comprises a conductive plug structure coupled adjacent to each of the first channel material and the second channel material, and a conductive line structure adjacent to the conductive plug structure. Methods of forming the apparatus, memory devices, and electronic systems are also described.

Abstract: Multi-gate metal-oxide-semiconductor (MOS) transistors and methods of operating such multi-gate MOS transistors are disclosed. In one embodiment, the multi-gate MOS transistor comprises a first gate associated with a first body factor and comprising a first gate electrode for applying a first gate voltage, and a second gate associated with a second body factor greater than or equal to the first body factor and comprising a second gate electrode for applying a second gate voltage. The multi-gate MOS transistor further comprises a body of semiconductor material between the first dielectric layer and the second dielectric layer, where the semiconductor body comprises a first channel region located close to the first dielectric layer and a second channel region located close to the second dielectric layer. The multi-gate MOS transistor still further comprises a source region and a drain region each having a conductivity type different from a conductivity type of the body.

Abstract: Multi-gate metal-oxide-semiconductor (MOS) transistors and methods of operating such multi-gate MOS transistors are disclosed. In one embodiment, the multi-gate MOS transistor comprises a first gate associated with a first body factor and comprising a first gate electrode for applying a first gate voltage, and a second gate associated with a second body factor greater than or equal to the first body factor and comprising a second gate electrode for applying a second gate voltage. The multi-gate MOS transistor further comprises a body of semiconductor material between the first dielectric layer and the second dielectric layer, where the semiconductor body comprises a first channel region located close to the first dielectric layer and a second channel region located close to the second dielectric layer. The multi-gate MOS transistor still further comprises a source region and a drain region each having a conductivity type different from a conductivity type of the body.