Abstract: Disclosed is an electronic system for resetting the voltage of a charge-sensitive pre-amplifier having input from an X-ray detector and output to an ADC. The pre-amplifier gain is increased so that the RMS ADC noise is less than 1% of a representative digitized X-ray signal. The reset logic is configured to avoid loss of X-ray counts and to prevent the pre-amplifier output being outside the allowable input range of the ADC. Reset is initiated when the pre-amplifier output rises above an upper level, which is below the maximum allowable ADC input. Reset is also initiated when a pile-up event is detected, provided that such reset will not cause the pre-amplifier output to fall below the minimum allowable ADC input. At each reset a known amount of charge is removed from the pre-amplifier, and the reset time is continuously adjusted to ensure that the charge amount does not drift.

Abstract: Disclosed is an electronic system for resetting the voltage of a charge-sensitive pre-amplifier having input from an X-ray detector and output to an ADC. The pre-amplifier gain is increased so that the RMS ADC noise is less than 1% of a representative digitized X-ray signal. The reset logic is configured to avoid loss of X-ray counts and to prevent the pre-amplifier output being outside the allowable input range of the ADC. Reset is initiated when the pre-amplifier output rises above an upper level, which is below the maximum allowable ADC input. Reset is also initiated when a pile-up event is detected, provided that such reset will not cause the pre-amplifier output to fall below the minimum allowable ADC input. At each reset a known amount of charge is removed from the pre-amplifier, and the reset time is continuously adjusted to ensure that the charge amount does not drift.

Abstract: Disclosed are circuits for automatic calibration of the gain of electronic amplification and digitization systems for use with X-ray detectors. The calibration is based on injecting predetermined pulses into the electronic system and deriving a calibration ratio based the digital value of their amplitude with the digital value of the same pulses, unamplified and digitized with a high accuracy reference ADC. All ADCs, as well as the DACs used to control the pulser amplitude are referenced to a single common reference voltage. Calibration for non-linearity of the gain is disclosed with an alternative embodiment for the same circuits.

Abstract: Disclosed is a circuit for controlling the temperature and the bias voltage of a detector used by an X-ray analytical instrument. The circuit uses a single common reference voltage for the temperature measurement and for all the ADCs and DACs in the circuit, resulting in reduced drift and improved reproducibility of detector temperature and bias voltage. ADCs with a larger number of bits are used to produce precision values of the temperature, the bias voltage, and their respective setpoints. The setpoints are digitally varied until the precision setpoint values correspond to desired values of temperature and bias setpoints.

Abstract: Disclosed is a circuit for controlling the temperature and the bias voltage of a detector used by an X-ray analytical instrument. The circuit uses a single common reference voltage for the temperature measurement and for all the ADCs and DACs in the circuit, resulting in reduced drift and improved reproducibility of detector temperature and bias voltage. ADCs with a larger number of bits are used to produce precision values of the temperature, the bias voltage, and their respective setpoints. The setpoints are digitally varied until the precision setpoint values correspond to desired values of temperature and bias setpoints.

Abstract: Methods and systems for determining latency across a bus, such as a PCIe bus, coupling a field programmable gate array (FPGA) and a processor having different time incrementation rates. Both the FPGA and the processor count clock ticks independently, and using a calibration offset and the two incrementation rates, the processor converts the FPGA clock ticks into processor clock ticks in order to determine latency across the bus.

Abstract: Disclosed is a circuit for controlling the temperature and the bias voltage of a detector used by an X-ray analytical instrument. The circuit uses a single common reference voltage for the temperature measurement and for all the ADCs and DACs in the circuit, resulting in reduced drift and improved reproducibility of detector temperature and bias voltage. ADCs with a larger number of bits are used to produce precision values of the temperature, the bias voltage, and their respective setpoints. The setpoints are digitally varied until the precision setpoint values correspond to desired values of temperature and bias setpoints.

Abstract: High volume data processing systems and methods are provided to enable ultra-low latency processing and distribution of data. The systems and methods can be implemented to service primary trading houses where microsecond delays can significantly impact performance and value. According to one aspect, the systems and methods are configured to process data from a variety of market data sources in a variety of formats, while maintaining target latencies of less than 1 microsecond. A matrix of FPGA nodes is configured to provide ultra-low latencies while enabling deterministic and distributed processing. In some embodiments, the matrix can be configured to provide consistent latencies even during microburst conditions. Further book building operations (determination of current holdings and assets) can occur under ultra-low latency timing, providing for near instantaneous risk management, management, and execution processes, even under micro-burst conditions.

Abstract: Disclosed is an electronic system for resetting the voltage of a charge-sensitive pre-amplifier having input from an X-ray detector and output to an ADC. The pre-amplifier gain is increased so that the RMS ADC noise is less than 1% of a representative digitized X-ray signal. The reset logic is configured to avoid loss of X-ray counts and to prevent the pre-amplifier output being outside the allowable input range of the ADC. Reset is initiated when the pre-amplifier output rises above an upper level, which is below the maximum allowable ADC input. Reset is also initiated when a pile-up event is detected, provided that such reset will not cause the pre-amplifier output to fall below the minimum allowable ADC input. At each reset a known amount of charge is removed from the pre-amplifier, and the reset time is continuously adjusted to ensure that the charge amount does not drift.

Abstract: Disclosed are circuits for automatic calibration of the gain of electronic amplification and digitization systems for use with X-ray detectors. The calibration is based on injecting predetermined pulses into the electronic system and deriving a calibration ratio based the digital value of their amplitude with the digital value of the same pulses, unamplified and digitized with a high accuracy reference ADC. All ADCs, as well as the DACs used to control the pulser amplitude are referenced to a single common reference voltage. Calibration for non-linearity of the gain is disclosed with an alternative embodiment for the same circuits.

Abstract: Disclosed is a circuit for controlling the temperature and the bias voltage of a detector used by an X-ray analytical instrument. The circuit uses a single common reference voltage for the temperature measurement and for all the ADCs and DACs in the circuit, resulting in reduced drift and improved reproducibility of detector temperature and bias voltage. ADCs with a larger number of bits are used to produce precision values of the temperature, the bias voltage, and their respective setpoints. The setpoints are digitally varied until the precision setpoint values correspond to desired values of temperature and bias setpoints.

Abstract: High volume data processing systems and methods are provided to enable ultra-low latency processing and distribution of data. The systems and methods can be implemented to service primary trading houses where microsecond delays can significantly impact performance and value. According to one aspect, the systems and methods are configured to process data from a variety of market data sources in a variety of formats, while maintaining target latencies of less than 1 microsecond. A matrix of FPGA nodes is configured to provide ultra-low latencies while enabling deterministic and distributed processing. In some embodiments, the matrix can be configured to provide consistent latencies even during microburst conditions. Further book building operations (determination of current holdings and assets) can occur under ultra-low latency timing, providing for near instantaneous risk management, management, and execution processes, even under micro-burst conditions.

Abstract: High volume data processing systems and methods are provided to enable ultra-low latency processing and distribution of data. The systems and methods can be implemented to service primary trading houses where microsecond delays can significantly impact performance and value. According to one aspect, the systems and methods are configured to process data from a variety of market data sources in a variety of formats, while maintaining target latencies of less than 1 microsecond. A matrix of FPGA nodes is configured to provide ultra-low latencies while enabling deterministic and distributed processing. In some embodiments, the matrix can be configured to provide consistent latencies even during micro burst conditions. Further book building operations (determination of current holdings and assets) can occur under ultra-low latency timing, providing for near instantaneous risk management, management, and execution processes, even under microburst conditions.

Abstract: Methods and systems for determining latency across a bus, such as a PCIe bus, coupling a field programmable gate array (FPGA) and a processor having different time incrementation rates. Both the FPGA and the processor count clock ticks independently, and using a calibration offset and the two incrementation rates, the processor converts the FPGA clock ticks into processor clock ticks in order to determine latency across the bus.

Abstract: High volume data processing systems and methods are provided to enable ultra-low latency processing and distribution of data. The systems and methods can be implemented to service primary trading houses where microsecond delays can significantly impact performance and value. According to one aspect, the systems and methods are configured to process data from a variety of market data sources in a variety of formats, while maintaining target latencies of less than 1 microsecond. A matrix of FPGA nodes is configured to provide ultra-low latencies while enabling deterministic and distributed processing. In some embodiments, the matrix can be to configured to provide consistent latencies even during microburst conditions. Further book building operations (determination of current holdings and assets) can occur under ultra-low latency timing, providing for near instantaneous risk management, management, and execution processes, even under micro-burst conditions.

Abstract: A very low latency processing device for source data relating to specific operations, the source data being transmitted via at least one communication network in the form of packets encoded according to a protocol particular to the specific operations and supported by the communication network, the processing device including at least one logic circuit configured to process the source data in an autonomous manner via a predetermined structure so that the transmission of data in the structure enables the packets to be received, their source data to be processed and the final data generated by the processing operation to be transmitted.

Abstract: Disclosed is a device for acquiring and monitoring over time the development of at least one product-related variable. Said device comprises a support (34) that is associated with the product and supports a set of at least one sensor (26) for measuring said variable and means (30, 32, 34) for processing the data output by the sensor so as to monitor the development of said variable relative to threshold values. Said processing means are provided with a file system (30) in which the data output by the sensor is stored and a management algorithm (32) that organizes storing of the data in the file system and manages retrieval of said data. The file system and the management algorithm are mounted within the support.