Abstract: An electronic circuit including a bipolar switching memory device including first and second electrodes at terminals of which a programming voltage can be applied, the circuit including: a first mechanism applying, to the first electrode, a data signal having, during a time period d, a constant state 0 or 1; a second mechanism applying, to the second electrode, a control signal that alternates, during time period d, between state 1 and state 0, the control signal being same regardless of the state in which the memory device is programmed; a selection device allowing a current to flow into the memory device during a programming time included in time period d; and a change of state of the control signal taking place during the programming time.

Abstract: Adiabatic logic circuit having a first and a second inputs, a first and a second outputs and at least one supply and synchronization input (Phi), with this circuit comprising: a first logic device comprising at least one first microelectromechanical and/or nanoelectromechanical switch, referred to as first mechanical switch, controlled by a first input and connected to the first output and to the supply and synchronization input, a second logic device opposite the first logic device comprising at least one second microelectromechanical or nanoelectromechanical switch, referred to as second mechanical switch, controlled by the second input and connected to the second output and to the supply and synchronization input, first and second devices for partial discharging connected respectively between the first output and the supply and synchronization input and between the second output and the supply and synchronization input.

Abstract: An electronic circuit including a bipolar switching memory device including first and second electrodes at terminals of which a programming voltage can be applied, the circuit including: a first mechanism applying, to the first electrode, a data signal having, during a time period d, a constant state 0 or 1; a second mechanism applying, to the second electrode, a control signal that alternates, during time period d, between state 1 and state 0, the control signal being same regardless of the state in which the memory device is programmed; a selection device allowing a current to flow into the memory device during a programming time included in time period d; and a change of state of the control signal taking place during the programming time.

Abstract: Neuromorphic circuits are multi-cell networks configured to imitate the behavior of biological neural networks. A neuromorphic circuit is provided which comprises a network of neurons each identified by a neuron address in the network, each neuron being able to receive and process at least one input signal and then later emit on an output of the neuron a signal representing an event which occurs inside the neuron, and a programmable memory composed of elementary memories each associated with a respective neuron. The elementary memory, which is a memory of post-synaptic addresses and weights, comprises an activation input linked by a conductor to the output of the associated neuron to directly receive an event signal emitted by this neuron without passing through an address encoder or decoder. The post-synaptic addresses extracted from an elementary memory activated by a neuron are applied, with associated synaptic weights, as inputs to the neural network.

Abstract: An integrated circuit may include a digital output port including a buffer stage that includes subassemblies of MOSFET transistors. One subassembly may include two pull-up transistors having sources connected to a common high voltage, and having drains connected to a common node connected to the output terminal. Another subassembly may include pull-down transistors having sources connected to a common low voltage, and having drains connected to the common node. The pull-up and pull-down transistors are formed in a thin semiconductor layer of an FDSOI substrate. The substrate may include a thick semiconductor layer and an oxide layer separating the thin and thick semiconductor layers. Areas of the thick semiconductor layer facing the pull-up and pull-down transistors may be connected to a circuit configured to vary a threshold voltage of the pull-up and pull-down transistors.

Abstract: Adiabatic logic circuit having a first and a second inputs, a first and a second outputs and at least one supply and synchronisation input (Phi), with this circuit comprising: a first logic device comprising at least one first microelectromechanical and/or nanoelectromechanical switch, referred to as first mechanical switch, controlled by a first input and connected to the first output and to the supply and synchronisation input, a second logic device opposite the first logic device comprising at least one second microelectromechanical or nanoelectromechanical switch, referred to as second mechanical switch, controlled by the second input and connected to the second output and to the supply and synchronisation input, first and second devices for partial discharging connected respectively between the first output and the supply and synchronisation input and between the second output and the supply and synchronisation input.

Abstract: The invention relates to the asynchronous communication of data in complex integrated systems, be it inside integrated circuit chips or between integrated circuit chips, for example in a compact stack of chips. According to the invention, the transmission is done on a single conductor of exchanges. The data are transmitted on this conductor in the form of at least three levels of potential, the first level representing a first value of data item transmitted, the second representing a second value of data item transmitted, and the third representing an inactive level. An acknowledgment signal is transmitted on the same exchange conductor as the data. This signal is preferably sent by the receiver in the form of the forcing of the exchange conductor by the receiver to the inactive potential level, the sender detecting this forcing.

Abstract: An integrated circuit may include a digital output port including a buffer stage that includes subassemblies of MOSFET transistors. One subassembly may include two pull-up transistors having sources connected to a common high voltage, and having drains connected to a common node connected to the output terminal. Another subassembly may include pull-down transistors having sources connected to a common low voltage, and having drains connected to the common node. The pull-up and pull-down transistors are formed in a thin semiconductor layer of an FDSOI substrate. The substrate may include a thick semiconductor layer and an oxide layer separating the thin and thick semiconductor layers. Areas of the thick semiconductor layer facing the pull-up and pull-down transistors may be connected to a circuit configured to vary a threshold voltage of the pull-up and pull-down transistors.

Abstract: Neuromorphic circuits are multi-cell networks configured to imitate the behavior of biological neural networks. A neuromorphic circuit is provided which comprises a network of neurons each identified by a neuron address in the network, each neuron being able to receive and process at least one input signal and then later emit on an output of the neuron a signal representing an event which occurs inside the neuron, and a programmable memory composed of elementary memories each associated with a respective neuron. The elementary memory, which is a memory of post-synaptic addresses and weights, comprises an activation input linked by a conductor to the output of the associated neuron to directly receive an event signal emitted by this neuron without passing through an address encoder or decoder. The post-synaptic addresses extracted from an elementary memory activated by a neuron are applied, with associated synaptic weights, as inputs to the neural network.

Abstract: A digital electronic circuit includes: a plurality of sequential elements; at least one data-conducting path connecting an input sequential element to a destination sequential element; a clock outputting a clock signal on a clock tree for setting the speed of the sequential elements; a monitoring device receiving, as an input, at least one data signal traveling on a conducting path and arriving at a destination sequential element, the monitoring device including: a module for defining at least one detection window according to the clock tree; and a detector for detecting a transition of each data signal received during a detection window; and wherein each detection window is defined so as to enable the detection or anticipation of a fault corresponding to a violation of the rise time or the maintenance time of a data signal relative to a clock signal edge received by the destination sequential element receiving the data signal.

Abstract: The invention relates to the asynchronous communication of data in complex integrated systems, be it inside integrated circuit chips or between integrated circuit chips, for example in a compact stack of chips. According to the invention, the transmission is done on a single conductor of exchanges. The data are transmitted on this conductor in the form of at least three levels of potential, the first level representing a first value of data item transmitted, the second representing a second value of data item transmitted, and the third representing an inactive level. An acknowledgment signal is transmitted on the same exchange conductor as the data. This signal is preferably sent by the receiver in the form of the forcing of the exchange conductor by the receiver to the inactive potential level, the sender detecting this forcing.

Abstract: A digital electronic circuit includes: a plurality of sequential elements; at least one data-conducting path connecting an input sequential element to a destination sequential element; a clock outputting a clock signal on a clock tree for setting the speed of the sequential elements; a monitoring device receiving, as an input, at least one data signal traveling on a conducting path and arriving at a destination sequential element, the monitoring device including: a module for defining at least one detection window according to the clock tree; and a detector for detecting a transition of each data signal received during a detection window; and wherein each detection window is defined so as to enable the detection or anticipation of a fault corresponding to a violation of the rise time or the maintenance time of a data signal relative to a clock signal edge received by the destination sequential element receiving the data signal.

Abstract: A method for testing a variable capacitance measurement system including a fixed voltage source, a variable capacitance sensor, and a circuit to process information output by this sensor. The method connects an electrically controllable electronic simulation device to replace the variable capacitance sensor, models the electrophysical behaviour of the sensor, and tests the system.

Abstract: A circuit for biasing the bulk of a MOS transistor, including a capacitive element connecting the bulk of the MOS transistor to a source of an voltage.

Abstract: A method for testing a variable capacitance measurement system including a fixed voltage source, a variable capacitance sensor, and a circuit to process information output by this sensor. The method connects an electrically controllable electronic simulation device to replace the variable capacitance sensor, models the electrophysical behaviour of the sensor, and tests the system.

Abstract: This invention relates to an improved microelectronic RAM memory device, provided with 4T or 6T cells made using the double gate technology and each associated with two word lines.

Abstract: An accelerometric measurement device with a return loop including accelerometer, a corrector generating a signal for correction of the position of the accelerometer, a closed return loop to apply this correction signal to the accelerometer, a detector to detect an error in operation of the accelerometer, and a modifying component making at least a first modification to operation of the corrector from its initial state to a modified operating state.

Abstract: A circuit for biasing the bulk of a MOS transistor, including a capacitive element connecting the bulk of the MOS transistor to a source of an A.C. voltage.

Abstract: Method for controlling an analogue switch including a transistor to which a variable analogue input voltage Vin is applied on a first terminal between a source terminal and a drain terminal of the transistor while a second terminal between the drain and the source terminal is at a variable output voltage VST, including the steps of: during a first phase, applying a first voltage to the transistor gate, the first voltage equal to a sum of or a difference between Vin and a first constant potential V1, and configured to make the transistor conduct; and during a second phase, applying a second voltage to the transistor gate, the second voltage equal to a sum of or a difference between VST, Vin and a second constant potential V2, and configured to block the transistor, the difference between the first voltage and the second voltage being constant.

Abstract: This invention relates to an improved microelectronic RAM memory device, provided with 4T or 6T cells made using the double gate technology and each associated with two word lines.