Abstract: A receiving device and a method for controlling playback of a media content stream, the receiving device comprising a media player and being associated with a conditional access module is configured to receive, process and play back the media content stream. The receiving device comprises a service selection module configured to receive a user command during playback of a current media content stream and to forward the user command to a media content stream input selector included in the conditional access module. The media content stream input selector is configured to stop reception of the current media content stream and to switch to an input receiving an additional media content stream at reception of the user command, the additional content media stream containing at least one chunk to be injected into the current media content stream, said at least one chunk being configured to pause playback of the current media stream at a time point following reception of the user command.

Abstract: A multimedia receiver and a method for managing switching reception of a first media content stream to a second media content stream. The multimedia receiver comprises a receiving device associated with a conditional access module and a media player configured to playback content from the first media content stream or the second media content stream. The receiving device is configured to receive a user command during playback of the first media content stream and to forward the user command to the conditional access module, the user command comprising at least one parameter defining reception of the second media content stream. The conditional access module is configured to up date, following reception of the user command, at least one descriptor in an information table associated with the first media content stream.

Abstract: The invention aims to provide a method and a system on chip able to detect at once hardware and software errors to prevent manipulations for retrieving cryptographic keys, inserting or suppressing instructions to bypass security processes, modifying programs or memory content etc. The system on chip comprises a core including at least two processors, registers, and a data consistency check module. The core is connected to at least one set of memories containing zones for instructions of a first program and of a second program, said instructions being to be executed respectively by the first and second processor, which respectively produce and store result data into the registers and the memories.

Abstract: The invention aims to provide a method and a system on chip able to detect at once hardware and software errors to prevent manipulations for retrieving cryptographic keys, inserting or suppressing instructions to bypass security processes, modifying programs or memory content etc. The system on chip comprises a core including at least two processors, registers, and a data consistency check module. The core is connected to at least one set of memories containing zones for instructions of a first program and of a second program, said instructions being to be executed respectively by the first and second processor, which respectively produce and store result data into the registers and the memories.

Abstract: The invention aims to provide a method and a system on chip able to detect at once hardware and software errors to prevent manipulations for retrieving cryptographic keys, inserting or suppressing instructions to bypass security processes, modifying programs or memory content etc. The system on chip comprises a core including at least two processors, registers, and a data consistency check module. The core is connected to at least one set of memories containing zones for instructions of a first program and of a second program, said instructions being to be executed respectively by the first and second processor, which respectively produce and store result data into the registers and the memories.

Abstract: The present invention describes a system and a method for securely loading digital information from an external storage device in a non-trusted environment into a memory module in a trusted environment within a data processing system. A master mode and a service mode are described, the master mode being when the secure loading is requested by a secure processor residing within the trusted environment and the service mode being when the loading is requested by an element which is external to the trusted environment i.e. in the non-trusted environment. The system comprises at least one storage device, one memory module and at least one first processor, and further comprises a memory access controller module connected between the processor and the memory module, and a secure memory management module connected to the processor, the memory module, the storage device and the memory access controller.

Abstract: The present invention describes a system and a method for securely loading digital information from an external storage device in a non-trusted environment into a memory module in a trusted environment within a data processing system. A master mode and a service mode are described, the master mode being when the secure loading is requested by a secure processor residing within the trusted environment and the service mode being when the loading is requested by an element which is external to the trusted environment i.e. in the non-trusted environment. The system comprises at least one storage device, one memory module and at least one first processor, and further comprises a memory access controller module connected between the processor and the memory module, and a secure memory management module connected to the processor, the memory module, the storage device and the memory access controller.

Abstract: The present invention describes a system and a method for securely loading digital information from a storage device into a memory module in a data processing system, said data processing system comprising at least one storage device, one memory module and at least one processor, said data processing system further comprising a memory access controller module connected between the processor and the memory module, and a secure memory management module connected to the processor, the memory module, the storage device and the memory access controller. Requests by the processor for data are passed to the secure memory management module, which loads the data from the storage device to the memory module and configures the memory access controller such that the processor will have access to the data.

Abstract: The invention aims to provide a method and a system on chip able to detect at once hardware and software errors to prevent manipulations for retrieving cryptographic keys, inserting or suppressing instructions to bypass security processes, modifying programs or memory content etc. The system on chip comprises a core including at least two processors, registers, and a data consistency check module. The core is connected to at least one set of memories containing zones for instructions of a first program and of a second program, said instructions being to be executed respectively by the first and second processor, which respectively produce and store result data into the registers and the memories.

Abstract: The present invention describes a system and a method for securely loading digital information from a storage device into a memory module in a data processing system, said data processing system comprising at least one storage device, one memory module and at least one processor, said data processing system further comprising a memory access controller module connected between the processor and the memory module, and a secure memory management module connected to the processor, the memory module, the storage device and the memory access controller. Requests by the processor for data are passed to the secure memory management module, which loads the data from the storage device to the memory module and configures the memory access controller such that the processor will have access to the data.

Abstract: The device (6) for the evaluation of algorithms comprises: