Abstract: Methods and apparatus relating to techniques for repeating graphics render pattern detection are described. In an embodiment, a repeating pattern in a plurality of workload blocks is detected. Information corresponding to the plurality of workload blocks is stored and analyzed to determine a Dynamic Voltage Frequency Scaling (DVFS) sampling window of a processor. Other embodiments are also disclosed and claimed.

Abstract: Methods, systems and apparatuses provide for technology that detects an access to memory, wherein the memory is on a discrete graphics device that includes an accelerator, sets an idle hysteresis value of the memory to a first level if the access to the memory is associated with activity in the accelerator, and sets the idle hysteresis value of the memory to a second level if the access to the memory is not associated with the activity in the accelerator, wherein the second level is greater than the first level.

Abstract: A system that includes first circuitries to operate at a first clock frequency, second circuitries to operate at a second clock frequency, and circuitry to adjust the first and second clock frequencies. In some examples, the circuitry is to selectively adjust the first and second clock frequencies provided to the respective first circuitries and the second circuitries according to a target ratio based on temperature and power consumption of the first circuitries and the second circuitries, wherein the target ratio is based on clock frequencies of the first circuitries and the second circuitries, stall time of the first circuitries, and dynamic capacitance of the first circuitries and the second circuitries.

Abstract: Disclosed herein are embodiments of systems and methods for stable and elevated idle-mode temperature for assembled semiconductor devices. In an embodiment, a processor includes a communication interface configured to receive, from a first hardware component, instructions assigned to the processor for execution. The processor also includes temperature-measurement circuitry configured to monitor an on-chip temperature of the processor. The processor also includes control logic configured to: determine whether the processor is active or idle; determine whether the on-chip temperature of the processor exceeds a first threshold; based on determining that the processor is idle and that the on-chip temperature of the processor exceeds the first threshold, disable one or more idle-mode power-saving features of the processor; and selectively adjust one or more operating parameters of the processor to keep the on-chip temperature of the processor between the first threshold and a second (higher) threshold.

Abstract: Methods and apparatus relating to advanced graphics Power State management are described. In one embodiment, measurement logic detects information about idle transitions and active transitions of a power-well of a processor. In turn, determination logic determines performance loss and/or energy gain based at least in part on the detected information and power-on latency of the power-well of the processor. Other embodiments are also disclosed and claimed.

Abstract: Methods and apparatus relating to techniques for repeating graphics render pattern detection are described. In an embodiment, a repeating pattern in a plurality of workload blocks is detected. Information corresponding to the plurality of workload blocks is stored and analyzed to determine a Dynamic Voltage Frequency Scaling (DVFS) sampling window of a processor. Other embodiments are also disclosed and claimed.

Abstract: Methods and apparatus relating to techniques for repeating graphics render pattern detection are described. In an embodiment, a repeating pattern in a plurality of workload blocks is detected. Information corresponding to the plurality of workload blocks is stored and analyzed to determine a Dynamic Voltage Frequency Scaling (DVFS) sampling window of a processor. Other embodiments are also disclosed and claimed.

Abstract: Methods and apparatus relating to techniques for runtime flip stability characterization are described. In an embodiment, logic circuitry determines the amount of work to be performed by a processor to render a pattern during each of a plurality of Vertical blank (Vblank) intervals. Memory stores information corresponding to a workload to be executed by the processor during each of the plurality of Vblank intervals. An operating frequency of the processor may then be modified based at least in part on analysis of the stored information to indicate which of the plurality of Vblank intervals would provide an improved stability for rendering the pattern. Other embodiments are also disclosed and claimed.

Abstract: Methods and apparatus relating to advanced graphics Power State management are described. In one embodiment, measurement logic detects information about idle transitions and active transitions of a power-well of a processor. In turn, determination logic determines performance loss and/or energy gain based at least in part on the detected information and power-on latency of the power-well of the processor. Other embodiments are also disclosed and claimed.

Abstract: Methods and apparatus relating to advanced graphics Power State management are described. In one embodiment, measurement logic detects information about idle transitions and active transitions of a power-well of a processor. In turn, determination logic determines performance loss and/or energy gain based at least in part on the detected information and power-on latency of the power-well of the processor. Other embodiments are also disclosed and claimed.

Abstract: Methods and apparatus relating to techniques for repeating graphics render pattern detection are described. In an embodiment, a repeating pattern in a plurality of workload blocks is detected. Information corresponding to the plurality of workload blocks is stored and analyzed to determine a Dynamic Voltage Frequency Scaling (DVFS) sampling window of a processor. Other embodiments are also disclosed and claimed.

Abstract: Methods and apparatus relating to techniques for runtime flip stability characterization are described. In an embodiment, logic circuitry determines the amount of work to be performed by a processor to render a pattern during each of a plurality of Vertical blank (Vblank) intervals. Memory stores information corresponding to a workload to be executed by the processor during each of the plurality of Vblank intervals. An operating frequency of the processor may then be modified based at least in part on analysis of the stored information to indicate which of the plurality of Vblank intervals would provide an improved stability for rendering the pattern. Other embodiments are also disclosed and claimed.

Abstract: Methods and apparatus relating to advanced graphics Power State management are described. In one embodiment, measurement logic detects information about idle transitions and active transitions of a power-well of a processor. In turn, determination logic determines performance loss and/or energy gain based at least in part on the detected information and power-on latency of the power-well of the processor. Other embodiments are also disclosed and claimed.

Abstract: Methods and apparatus relating to advanced graphics Power State management are described. In one embodiment, measurement logic detects information about idle transitions and active transitions of a power-well of a processor. In turn, determination logic determines performance loss and/or energy gain based at least in part on the detected information and power-on latency of the power-well of the processor. Other embodiments are also disclosed and claimed.

Abstract: One embodiment provides an apparatus. The apparatus includes a graphics processor and power management logic. The graphics processor includes display engine logic and encoder logic. The power management logic is to adjust an operating frequency of the encoder logic based, at least in part, on an encode time duration and based, at least in part, on a frame period.

Abstract: Methods and apparatus relating to advanced graphics Power State management are described. In one embodiment, measurement logic detects information about idle transitions and active transitions of a power-well of a processor. In turn, determination logic determines performance loss and/or energy gain based at least in part on the detected information and power-on latency of the power-well of the processor. Other embodiments are also disclosed and claimed.

Abstract: One or more system, apparatus, method, and computer readable media is described below for power management of one or more graphics processor resources. In some embodiments, a graphics processor context associated with an application an including power-related hardware configuration and control parameters is stored to memory. In some embodiments, graphics processor contexts are switched in and out as different application workloads are processed by resources of the graphics processor. In some embodiments, power-performance management algorithms are grouped and sequentially executed in ordered phases of a control loop to generate a compatible set of control parameter requests. Once finalized, the set is output as requests to graphics processor hardware and/or updates to stored graphics processor contexts.

Abstract: Methods and apparatus relating to advanced graphics Power State management are described. In one embodiment, measurement logic detects information about idle transitions and active transitions of a power-well of a processor. In turn, determination logic determines performance loss and/or energy gain based at least in part on the detected information and power-on latency of the power-well of the processor. Other embodiments are also disclosed and claimed.

Abstract: One or more system, apparatus, method, and computer readable media is described below for power management of one or more graphics processor resources. In some embodiments, a graphics processor context associated with an application an including power-related hardware configuration and control parameters is stored to memory. In some embodiments, graphics processor contexts are switched in and out as different application workloads are processed by resources of the graphics processor. In some embodiments, power-performance management algorithms are grouped and sequentially executed in ordered phases of a control loop to generate a compatible set of control parameter requests. Once finalized, the set is output as requests to graphics processor hardware and/or updates to stored graphics processor contexts.

Abstract: Methods and apparatus relating to techniques for dynamically selecting optimum graphics logic frequency and/or graphics logic power gating configuration are described. In an embodiment, multi-rate control logic determines processor active slice count and processor frequency based at least in part on a target Frames Per Second (FPS) value and a current FPS value. The multi-rate control logic includes slow rate control logic to determine slice gating and operating frequency and a fast rate control logic to determine operating frequency of the processor. Other embodiments are also disclosed and claimed.