Abstract: A fully digital pulse width modulator substantially doubles resolution in a laser printer by outputting data to the laser on both the rising and falling edges of the clock cycle. A counter and the clock itself are used to select input to a multiplexer, and consequently, the data output to the laser from the multiplexer. A data selector code, generated by concatenating the binary value of the counter and the inverted clock bitwise, selects which of the 16 bits representing a pixel to place onto the data line, so that all 16 bits are output to the laser serially and sequentially in eight clock cycles. By using both the rising and falling edges of a clock cycle, the clock speed of the device is effectively doubled, without increasing actual clock speed. Device resolution is improved simply and inexpensively without major modification of printed circuit boards.

Abstract: A fully digital pulse width modulator substantially doubles resolution in a laser printer by outputting data to the laser on both the rising and falling edges of the clock cycle. A counter and the clock itself are used to select input to a multiplexer, and consequently, the data output to the laser from the multiplexer. A data selector code, generated by concatenating the binary value of the counter and the inverted clock bitwise, selects which of the 16 bits representing a pixel to place onto the data line, so that all 16 bits are output to the laser serially and sequentially in eight clock cycles. By using both the rising and falling edges of a clock cycle, the clock speed of the device is effectively doubled, without increasing actual clock speed. Device resolution is improved simply and inexpensively without major modification of printed circuit boards.

Abstract: A fully digital pulse width modulator substantially doubles resolution in a laser printer by outputting data to the laser on both the rising and falling edges of the clock cycle. A counter and the clock itself are used to select input to a multiplexer, and consequently, the data output to the laser from the multiplexer. A data selector code, generated by concatenating the binary value of the counter and the inverted clock bitwise, selects which of the 16 bits representing a pixel to place onto the data line, so that all 16 bits are output to the laser serially and sequentially in eight clock cycles. By using both the rising and falling edges of a clock cycle, the clock speed of the device is effectively doubled, without increasing actual clock speed. Device resolution is improved simply and inexpensively without major modification of printed circuit boards.

Abstract: Simple digital devices and methods are described for reducing electromagnetic interference even where a clock signal to the device is rapidly turned ON and OFF. A primary clock signal drives a signal selector. A signal delay is included to provide delayed clock pulse signals. The signal delay detunes the primary clock signal. By repeatedly switching the delay in and out of the clock signal path, a first signal is generated having a frequency at or about the clock signal, and, a second signal is generated which is displaced slightly from the first signal, but still at or about the clock frequency. By repeatedly switching the delay in and out of the primary clock signal path at a rate greater than the frequency of the clock signal, smaller portions of each primary clock pulse may be parsed for subsequent reaggregation to create a spread spectrum clock signal.

Abstract: A digital spread spectrum system provides a simple, digital device and method for reducing electromagnetic interference even where a clock signal to the device is rapidly turned on and off. A primary clock signal drives a signal selector. A signal delay is provided in the circuit to provide delayed clock pulse signals. The signal delay detunes the primary clock signal. By repeatedly switching the delay in and out of the clock signal path, a first signal is generated having a frequency at or about the clock signal, and, a second signal is generated which is displaced slightly from the first signal, but still at or about the clock frequency. By repeatedly switching the delay in and out of the primary clock signal path at a rate greater than the frequency of the clock signal, smaller portions of each primary clock pulse may be parsed for subsequent reaggregation to create a spread spectrum clock signal.

Abstract: A fully digital pulse width modulator substantially doubles resolution in a laser printer b y outputting data to the laser on both the rising and falling edges of the clock cycle. A counter and the clock itself are used to select input to a multiplexer, and consequently, the data output to the laser from the multiplexer. A data selector code, generated b y concatenating the binary value of the counter and the inverted clock bitwise, selects which of the 16 bits representing a pixel to place onto the data line, so that all 16 bits are output to the laser serially and sequentially in eight clock cycles. By using both the rising and falling edges of a clock cycle, the clock speed of the device is effectively doubled, without increasing actual clock speed. Device resolution is improved simply and inexpensively without major modification of printed circuit boards.

Abstract: A method and system are provided for converting image data between planar format and a chunky format. A barrel shifter sorts the image bytes by color plane for output to a plurality of memory cells. Two addresses of each memory cell are not interconnected and function as a set of selection lines, whose binary values determine the number of positions that the data stored in the memory cells are shifted in response to the action of the barrel shifter. The sorted bytes are stored according to color format in the remaining, interconnected addresses of the memory cells. When the barrel shifter does not shift the bytes in a word, cyan bytes are stored in the memory cells. When the barrel shifter shifts the word one byte position, magenta bytes are output to the memory cells. Yellow and black bytes, respectively, are output for shifts of two bytes and three bytes, respectively. Each color plane is therefore stored in a separate memory cell and the chunky format data are converted to a planar format.

Abstract: An arrangement for producing a variable width pulse is disclosed for use in an electrostatic printing mechanism which is adapted to produce grayscale intensity of a pixel to be printed based on predetermined digital data. The variable width pulse is formed during a clock interval which is established by a clock signal such that the width of the pulse during the clock interval is based on the digital data and corresponds to a grayscale intensity of the pixel to be printed. The arrangement includes at least a first delay line including an input, an output and a plurality of cells serially connected therebetween such that a digital signal received by the input propagates from the input to the output through the cells. Each cell includes a cell output for indication of the present state of digital data contained in the cell. A pulse generating section then provides the clock signal, as the digital signal, to the input of the first delay line such that the clock signal propagates through the first delay line.

Abstract: A programmable DMA controller that uses an instruction set dedicated to moving data efficiently over a bus, comprising a program memory, a program counter, a FIFO memory, a bus buffer, registers, an accumulator, and an ALU. The DMA controller instruction set comprises the following instructions: load, move, add, subtract, branch on zero, branch on not zero, lock, and interrupt. Another DMA controller embodiment uses a SIMD processor. In operation, a CPU downloads DMA programs to the DMA controller. The DMA controller stores these programs in its program memory. The CPU signals the DMA to begin a DMA transfer operation. The ALU and associated devices execute the program instructions to perform the desired DMA transfer. The DMA controller then sends an interrupt to the CPU to indicate the DMA transfer is complete.