Abstract: An interface circuit makes it possible, starting from an input signal varying between a reference level (VR) available on a first terminal and a first voltage level (V1), to deliver an output signal varying between this reference level (VR) and a second voltage level (V2) available on a second terminal. The circuit includes first and second branches each including first and second serially connected complementary transistors and a third branch with serially connected first and second transistors. First and second inverters couple the input terminal to respective control electrodes of the second transistors in the second and third branches. The inverters have response times chosen so that the two transistors of the third branch are never on simultaneously. Thus, short-circuiting the transistors of the second branch during the transient regime creates almost no current spike.