Patents by Inventor Marc. C. French
Marc. C. French has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11626519Abstract: Embodiments of the invention include non-planar InGaZnO (IGZO) transistors and methods of forming such devices. In an embodiment, the IGZO transistor may include a substrate and source and drain regions formed over the substrate. According to an embodiment, an IGZO layer may be formed above the substrate and may be electrically coupled to the source region and the drain region. Further embodiments include a gate electrode that is separated from the IGZO layer by a gate dielectric. In an embodiment, the gate dielectric contacts more than one surface of the IGZO layer. In one embodiment, the IGZO transistor is a finfet transistor. In another embodiment the IGZO transistor is a nanowire or a nanoribbon transistor. Embodiments of the invention may also include a non-planar IGZO transistor that is formed in the back end of line stack (BEOL) of an integrated circuit chip.Type: GrantFiled: October 19, 2020Date of Patent: April 11, 2023Assignee: Intel CorporationInventors: Van H. Le, Gilbert Dewey, Rafael Rios, Jack T. Kavalieros, Marko Radosavljevic, Kent E. Millard, Marc C. French, Ashish Agrawal, Benjamin Chu-Kung, Ryan E. Arch
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Patent number: 11450527Abstract: An apparatus including a transistor device including a channel including germanium disposed on a substrate; a buffer layer disposed on the substrate between the channel and the substrate, wherein the buffer layer includes silicon germanium; and a seed layer disposed on the substrate between the buffer layer and the substrate, wherein the seed layer includes germanium. A method including forming seed layer on a silicon substrate, wherein the seed layer includes germanium; forming a buffer layer on the seed layer, wherein the buffer layer includes silicon germanium; and forming a transistor device including a channel on the buffer layer.Type: GrantFiled: July 2, 2016Date of Patent: September 20, 2022Assignee: Intel CorporationInventors: Van H. Le, Benjamin Chu-Kung, Willy Rachmady, Marc C. French, Seung Hoon Sung, Jack T. Kavalieros, Matthew V. Metz, Ashish Agrawal
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Publication number: 20210050455Abstract: Embodiments of the invention include non-planar InGaZnO (IGZO) transistors and methods of forming such devices. In an embodiment, the IGZO transistor may include a substrate and source and drain regions formed over the substrate. According to an embodiment, an IGZO layer may be formed above the substrate and may be electrically coupled to the source region and the drain region. Further embodiments include a gate electrode that is separated from the IGZO layer by a gate dielectric. In an embodiment, the gate dielectric contacts more than one surface of the IGZO layer. In one embodiment, the IGZO transistor is a finfet transistor. In another embodiment the IGZO transistor is a nanowire or a nanoribbon transistor. Embodiments of the invention may also include a non-planar IGZO transistor that is formed in the back end of line stack (BEOL) of an integrated circuit chip.Type: ApplicationFiled: October 19, 2020Publication date: February 18, 2021Inventors: Van H. LE, Gilbert DEWEY, Rafael RIOS, Jack T. KAVALIEROS, Marko RADOSAVLJEVIC, Kent E. MILLARD, Marc C. FRENCH, Ashish AGRAWAL, Benjamin CHU-KUNG, Ryan E. ARCH
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Patent number: 10847656Abstract: Embodiments of the invention include non-planar InGaZnO (IGZO) transistors and methods of forming such devices. In an embodiment, the IGZO transistor may include a substrate and source and drain regions formed over the substrate. According to an embodiment, an IGZO layer may be formed above the substrate and may be electrically coupled to the source region and the drain region. Further embodiments include a gate electrode that is separated from the IGZO layer by a gate dielectric. In an embodiment, the gate dielectric contacts more than one surface of the IGZO layer. In one embodiment, the IGZO transistor is a finfet transistor. In another embodiment the IGZO transistor is a nanowire or a nanoribbon transistor. Embodiments of the invention may also include a non-planar IGZO transistor that is formed in the back end of line stack (BEOL) of an integrated circuit chip.Type: GrantFiled: December 23, 2015Date of Patent: November 24, 2020Assignee: Intel CorporationInventors: Van H. Le, Gilbert Dewey, Rafael Rios, Jack T. Kavalieros, Marko Radosavljevic, Kent E. Millard, Marc C. French, Ashish Agrawal, Benjamin Chu-Kung, Ryan E. Arch
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Publication number: 20200066515Abstract: An apparatus including a transistor device including a channel including germanium disposed on a substrate; a buffer layer disposed on the substrate between the channel and the substrate, wherein the buffer layer includes silicon germanium; and a seed layer disposed on the substrate between the buffer layer and the substrate, wherein the seed layer includes germanium. A method including forming seed layer on a silicon substrate, wherein the seed layer includes germanium; forming a buffer layer on the seed layer, wherein the buffer layer includes silicon germanium; and forming a transistor device including a channel on the buffer layer.Type: ApplicationFiled: July 2, 2016Publication date: February 27, 2020Inventors: Van H. LE, Benjamin CHU-KUNG, Willy RACHMADY, Marc C. FRENCH, Seung Hoon SUNG, Jack T. KAVALIEROS, Matthew V. METZ, Ashish AGRAWAL
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Patent number: 10249742Abstract: A method including forming a non-planar conducting channel of a device between junction regions on a substrate, the substrate including a blocking material beneath the channel, the blocking material including a property to inhibit carrier leakage; and forming a gate stack on the channel, the gate stack including a dielectric material and a gate electrode. A method including forming a buffer material on a semiconductor substrate, the buffer material including a semiconductor material including a different lattice structure than the substrate; forming a blocking material on the buffer material, the blocking material including a property to inhibit carrier leakage; and forming a transistor device on the substrate. An apparatus including a non-planar multi-gate device on a substrate including a transistor device including a channel disposed on a substrate including a blocking material beneath the channel, the blocking material including a property to inhibit carrier leakage.Type: GrantFiled: June 27, 2015Date of Patent: April 2, 2019Assignee: Intel CorporationInventors: Van H. Le, Gilbert Dewey, Benjamin Chu-Kung, Ashish Agrawal, Matthew V. Metz, Willy Rachmady, Marc C. French, Jack T. Kavalieros, Rafael Rios, Seiyon Kim, Seung Hoon Sung, Sanaz K. Gardner, James M. Powers, Sherry R. Taft
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Publication number: 20190058043Abstract: Disclosed herein are transistor gate-channel arrangements, and related methods and devices. For example, in some embodiments, a transistor gate-channel arrangement may include a channel material and a transistor gate stack. The transistor gate stack may include a gate electrode material, a high-k dielectric disposed between the gate electrode material and the channel material, and indium gallium zinc oxide (IGZO) disposed between the high-k dielectric material and the channel material.Type: ApplicationFiled: March 30, 2016Publication date: February 21, 2019Applicant: Intel CorporationInventors: Gilbert W. Dewey, Rafael Rios, Shriram Shivaraman, Marko Radosavljevic, Kent E. Millard, Marc C. French, Van H. Le
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Publication number: 20180366587Abstract: Embodiments of the invention include non-planar InGaZnO (IGZO) transistors and methods of forming such devices. In an embodiment, the IGZO transistor may include a substrate and source and drain regions formed over the substrate. According to an embodiment, an IGZO layer may be formed above the substrate and may be electrically coupled to the source region and the drain region. Further embodiments include a gate electrode that is separated from the IGZO layer by a gate dielectric. In an embodiment, the gate dielectric contacts more than one surface of the IGZO layer. In one embodiment, the IGZO transistor is a finfet transistor. In another embodiment the IGZO transistor is a nanowire or a nanoribbon transistor. Embodiments of the invention may also include a non-planar IGZO transistor that is formed in the back end of line stack (BEOL) of an integrated circuit chip.Type: ApplicationFiled: December 23, 2015Publication date: December 20, 2018Inventors: Van H. LE, Gilbert DEWEY, Rafael RIOS, Jack T. KAVALIEROS, Marko RADOSAVLJEVIC, Kent E. MILLARD, Marc C. FRENCH, Ashish AGRAWAL, Benjamin CHU-KUNG, Ryan E. ARCH
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Patent number: 10008565Abstract: Semiconductor device stacks and devices made there from having Ge-rich device layers. A Ge-rich device layer is disposed above a substrate, with a p-type doped Ge etch suppression layer (e.g., p-type SiGe) disposed there between to suppress etch of the Ge-rich device layer during removal of a sacrificial semiconductor layer richer in Si than the device layer. Rates of dissolution of Ge in wet etchants, such as aqueous hydroxide chemistries, may be dramatically decreased with the introduction of a buried p-type doped semiconductor layer into a semiconductor film stack, improving selectivity of etchant to the Ge-rich device layers.Type: GrantFiled: June 16, 2017Date of Patent: June 26, 2018Assignee: Intel CorporationInventors: Willy Rachmady, Van H. Le, Ravi Pillarisetty, Jessica S. Kachian, Marc C. French, Aaron A. Budrevich
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Publication number: 20180158933Abstract: A method including forming a non-planar conducting channel of a device between junction regions on a substrate, the substrate including a blocking material beneath the channel, the blocking material including a property to inhibit carrier leakage; and forming a gate stack on the channel, the gate stack including a dielectric material and a gate electrode. A method including forming a buffer material on a semiconductor substrate, the buffer material including a semiconductor material including a different lattice structure than the substrate; forming a blocking material on the buffer material, the blocking material including a property to inhibit carrier leakage; and forming a transistor device on the substrate. An apparatus including a non-planar multi-gate device on a substrate including a transistor device including a channel disposed on a substrate including a blocking material beneath the channel, the blocking material including a property to inhibit carrier leakage.Type: ApplicationFiled: June 27, 2015Publication date: June 7, 2018Inventors: Van H. LE, Gilbert DEWEY, Benjamin CHU-KUNG, Ashish AGRAWAL, Matthew V. METZ, Willy RACHMADY, Marc C. FRENCH, Jack T. KAVALIEROS, Rafael RIOS, Seiyon KIM, Seung Hoon SUNG, Sanaz K. GARDNER, James M. POWERS, Sherry R. TAFT
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Publication number: 20170317187Abstract: An embodiment includes a device comprising: first and second fins adjacent one another and each including channel and subfin layers, the channel layers having bottom surfaces directly contacting upper surfaces of the subfin layers; wherein (a) the bottom surfaces are generally coplanar with one another and are generally flat; (b) the upper surfaces are generally coplanar with one another and are generally flat; and (c) the channel layers include an upper material and the subfin layers include a lower III-V material different from the upper III-V material. Other embodiments are described herein.Type: ApplicationFiled: December 23, 2014Publication date: November 2, 2017Inventors: Sanaz K. GARDNER, Willy RACHMADY, Matthew V. METZ, Gilbert DEWEY, Jack T. KAVALIEROS, Chandra S. MOHAPATRA, Anand S. MURTHY, Nadia RAHHAL-ORABI, Nancy M. ZELICK, Marc C. FRENCH, Tahir GHANI
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Publication number: 20170288019Abstract: Semiconductor device stacks and devices made there from having Ge-rich device layers. A Ge-rich device layer is disposed above a substrate, with a p-type doped Ge etch suppression layer (e.g., p-type SiGe) disposed there between to suppress etch of the Ge-rich device layer during removal of a sacrificial semiconductor layer richer in Si than the device layer. Rates of dissolution of Ge in wet etchants, such as aqueous hydroxide chemistries, may be dramatically decreased with the introduction of a buried p-type doped semiconductor layer into a semiconductor film stack, improving selectivity of etchant to the Ge-rich device layers.Type: ApplicationFiled: June 16, 2017Publication date: October 5, 2017Inventors: Willy RACHMADY, Van H. LE, Ravi PILLARISETTY, Jessica S. KACHIAN, Marc C. FRENCH, Aaron A. BUDREVICH
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Patent number: 9691848Abstract: Semiconductor device stacks and devices made there from having Ge-rich device layers. A Ge-rich device layer is disposed above a substrate, with a p-type doped Ge etch suppression layer (e.g., p-type SiGe) disposed there between to suppress etch of the Ge-rich device layer during removal of a sacrificial semiconductor layer richer in Si than the device layer. Rates of dissolution of Ge in wet etchants, such as aqueous hydroxide chemistries, may be dramatically decreased with the introduction of a buried p-type doped semiconductor layer into a semiconductor film stack, improving selectivity of etchant to the Ge-rich device layers.Type: GrantFiled: October 25, 2016Date of Patent: June 27, 2017Assignee: Intel CorporationInventors: Willy Rachmady, Van H. Le, Ravi Pillarisetty, Jessica S. Kachian, Marc C. French, Aaron A. Budrevich
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Publication number: 20170047401Abstract: Semiconductor device stacks and devices made there from having Ge-rich device layers. A Ge-rich device layer is disposed above a substrate, with a p-type doped Ge etch suppression layer (e.g., p-type SiGe) disposed there between to suppress etch of the Ge-rich device layer during removal of a sacrificial semiconductor layer richer in Si than the device layer. Rates of dissolution of Ge in wet etchants, such as aqueous hydroxide chemistries, may be dramatically decreased with the introduction of a buried p-type doped semiconductor layer into a semiconductor film stack, improving selectivity of etchant to the Ge-rich device layers.Type: ApplicationFiled: October 25, 2016Publication date: February 16, 2017Inventors: Willy Rachmady, Van H. LE, Ravi PILLARISETTY, Jessica S. KACHIAN, Marc C. FRENCH, Aaron A. BUDREVICH
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Patent number: 9490329Abstract: Semiconductor device stacks and devices made there from having Ge-rich device layers. A Ge-rich device layer is disposed above a substrate, with a p-type doped Ge etch suppression layer (e.g., p-type SiGe) disposed there between to suppress etch of the Ge-rich device layer during removal of a sacrificial semiconductor layer richer in Si than the device layer. Rates of dissolution of Ge in wet etchants, such as aqueous hydroxide chemistries, may be dramatically decreased with the introduction of a buried p-type doped semiconductor layer into a semiconductor film stack, improving selectivity of etchant to the Ge-rich device layers.Type: GrantFiled: October 13, 2015Date of Patent: November 8, 2016Assignee: Intel CorporationInventors: Willy Rachmady, Van H. Le, Ravi Pillarisetty, Jessica S. Kachian, Marc C. French, Aaron A. Budrevich
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Publication number: 20160049476Abstract: Semiconductor device stacks and devices made there from having Ge-rich device layers. A Ge-rich device layer is disposed above a substrate, with a p-type doped Ge etch suppression layer (e.g., p-type SiGe) disposed there between to suppress etch of the Ge-rich device layer during removal of a sacrificial semiconductor layer richer in Si than the device layer. Rates of dissolution of Ge in wet etchants, such as aqueous hydroxide chemistries, may be dramatically decreased with the introduction of a buried p-type doped semiconductor layer into a semiconductor film stack, improving selectivity of etchant to the Ge-rich device layers.Type: ApplicationFiled: October 13, 2015Publication date: February 18, 2016Inventors: Willy Rachmady, Van H. Le, Ravi Pillarisetty, Jessica S. Kachian, Marc C. French, Aaron A. Budrevich
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Patent number: 9159787Abstract: Semiconductor device stacks and devices made there from having Ge-rich device layers. A Ge-rich device layer is disposed above a substrate, with a p-type doped Ge etch suppression layer (e.g., p-type SiGe) disposed there between to suppress etch of the Ge-rich device layer during removal of a sacrificial semiconductor layer richer in Si than the device layer. Rates of dissolution of Ge in wet etchants, such as aqueous hydroxide chemistries, may be dramatically decreased with the introduction of a buried p-type doped semiconductor layer into a semiconductor film stack, improving selectivity of etchant to the Ge-rich device layers.Type: GrantFiled: June 10, 2014Date of Patent: October 13, 2015Assignee: Intel CorporationInventors: Willy Rachmady, Van H. Le, Ravi Pillarisetty, Jessica S. Kachian, Marc C. French, Aaron A. Budrevich
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Publication number: 20140291772Abstract: Semiconductor device stacks and devices made there from having Ge-rich device layers. A Ge-rich device layer is disposed above a substrate, with a p-type doped Ge etch suppression layer (e.g., p-type SiGe) disposed there between to suppress etch of the Ge-rich device layer during removal of a sacrificial semiconductor layer richer in Si than the device layer. Rates of dissolution of Ge in wet etchants, such as aqueous hydroxide chemistries, may be dramatically decreased with the introduction of a buried p-type doped semiconductor layer into a semiconductor film stack, improving selectivity of etchant to the Ge-rich device layers.Type: ApplicationFiled: June 10, 2014Publication date: October 2, 2014Inventors: Willy RACHMADY, Van H. Le, Ravi Pillarisetty, Jessica S. Kachian, Marc C. French, Aaron A. Budrevich
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Patent number: 8785907Abstract: An embodiment includes depositing a material onto a substrate where the material includes a different lattice constant than the substrate (e.g., III-V or IV epitaxial (EPI) material on a Si substrate). An embodiment includes an EPI layer formed within a trench having walls that narrow as the trench extends upwards. An embodiment includes an EPI layer formed within a trench using multiple growth temperatures. A defect barrier, formed in the EPI layer when the temperature changes, contains defects within the trench and below the defect barrier. The EPI layer above the defect barrier and within the trench is relatively defect free. An embodiment includes an EPI layer annealed within a trench to induce defect annihilation. An embodiment includes an EPI superlattice formed within a trench and covered with a relatively defect free EPI layer (that is still included in the trench). Other embodiments are described herein.Type: GrantFiled: December 20, 2012Date of Patent: July 22, 2014Assignee: Intel CorporationInventors: Niti Goel, Niloy Mukherjee, Seung Hoon Sung, Van H. Le, Matthew V. Metz, Jack T. Kavalieros, Ravi Pillarisetty, Sanaz K. Gardner, Sansaptak Dasgupta, Willy Rachmady, Benjamin Chu-Kung, Marko Radosavljevic, Gilbert Dewey, Marc C. French, Jessica Kachian, Satyarth Suri, Robert S. Chau
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Publication number: 20140167108Abstract: Semiconductor device stacks and devices made there from having Ge-rich device layers. A Ge-rich device layer is disposed above a substrate, with a p-type doped Ge etch suppression layer (e.g., p-type SiGe) disposed there between to suppress etch of the Ge-rich device layer during removal of a sacrificial semiconductor layer richer in Si than the device layer. Rates of dissolution of Ge in wet etchants, such as aqueous hydroxide chemistries, may be dramatically decreased with the introduction of a buried p-type doped semiconductor layer into a semiconductor film stack, improving selectivity of etchant to the Ge-rich device layers.Type: ApplicationFiled: December 17, 2012Publication date: June 19, 2014Inventors: Willy RACHMADY, Van H. LE, Ravi PILLARISETTY, Jessica S. KACHIAN, Marc C. FRENCH, Aaron A. BUDREVICH