Abstract: The subject of the present invention is a cryptographic system, having two inverse permutations, which can be implemented in a (micro) computer whose data processing resources are relatively limited. The two inverse permutations are processed with one and the same table, and the data zones, before and after permutation, occupy only one and the same memory zone. Applied to the DES cryptographic system, this can in particular be implemented in the memory card for the purpose of ensuring the security of transmissions between the card and a communication system; in particular the card reader of this system.

Abstract: A fast, parallel operating device for multiplying binary coded numbers. The numbers are divided into groups of n bits of directly successive significance levels. Subsequently, all feasible combinations of one group of the first number and one group of the second number are formed, for each combination a partial product being formed in a first array of partial product forming devices. A partial product is preferably formed by a logic circuit which operates non-sequentially but exclusively combinatory, and which has a logical depth of only three gates. The partial products are subsequently applied to a second array of partial sum forming devices in which they are added together with intermediate partial sums, taking into account their relative significance levels. Together with the partial product digit of lowest significance, the final row of partial sum forming devices then generates, co-operating in parallel, the complete product.