Abstract: The present disclosure concerns a method for fabricating a magnetoresistive element comprising a magnetic tunnel junction including a tunnel barrier layer, a first ferromagnetic layer and a second ferromagnetic layer; a writing current layer; and an interconnect layer configured for supplying the writing current to the writing current layer. A gap is provided in the interconnect layer such that the latter comprises two discontinuous interconnect segments extending along a layer plane and connecting the writing current layer in series. The method comprises: depositing the interconnect layer, writing current layer, second ferromagnetic layer, tunnel barrier layer and first ferromagnetic layer; forming the gap in the interconnect layer; filling the gap with the gap material; and forming the pillar by performing a single etch step until the interconnect layer, acting as a stop layer, is reached.

Abstract: A SOT-MRAM cell, comprising at least one magnetic tunnel junction (MTJ) comprising a tunnel barrier layer between a pinned ferromagnetic layer and a free ferromagnetic layer; a SOT line, extending substantially parallel to the plane of the layers and contacting a first end of said at least one MTJ; at least a first source line connected to one end of the SOT line; at least a first bit line and a second bit line, wherein the SOT-MRAM cell comprises one MTJ, each bit line being connected to the other end of the MTJ; or wherein the SOT-MRAM cell comprises two MTJs, each MTJ being connected to one of the first bit line and second bit line.

Abstract: A magnetic memory (MRAM) cell, comprising: a first layer formed from a substantially electrically conductive material; and a magnetic tunnel junction (MTJ) stack formed over the first layer, wherein the MTJ stack comprises: a ferromagnetic reference layer having an in-plane reference magnetization; a tunnel barrier layer; and a ferromagnetic storage layer between the tunnel barrier layer and the first layer, the storage layer having an in-plane storage magnetization; wherein the MTJ stack comprises an arrangement for providing an in-plane uniaxial anisotropy in the storage layer; wherein said in-plane uniaxial anisotropy makes an angle with the direction of the write current that is between 5° and 90°, and wherein said in-plane uniaxial anisotropy has an energy between 40 and 200 kBT and wherein coercivity is larger than 200 Oe.

Abstract: A memory device may comprise a substrate defining a main plane; a plurality of memory cells each comprising a SOT current layer disposed in the main plane of the substrate and a magnetic tunnel junction residing on the SOT current layer; and a bit line and a source line to flow a write current in a write path including the SOT current layer of a selected memory cell. The source line comprises a conductive magnetic material providing a magnetic bias field extending to the magnetic tunnel junction of the selected memory cell for assisting the switching of the cell state when the write current is flowing.

Abstract: A memory device may comprise a substrate defining a main plane; a plurality of memory cells each comprising a SOT current layer disposed in the main plane of the substrate and a magnetic tunnel junction residing on the SOT current layer; and a bit line and a source line to flow a write current in a write path including the SOT current layer of a selected memory cell. The source line comprises a conductive magnetic material providing a magnetic bias field extending to the magnetic tunnel junction of the selected memory cell for assisting the switching of the cell state when the write current is flowing.

Abstract: The present disclosure concerns a method for fabricating a magnetoresistive element comprising a magnetic tunnel junction including a tunnel barrier layer, a first ferromagnetic layer and a second ferromagnetic layer; a writing current layer; and an interconnect layer configured for supplying the writing current to the writing current layer. A gap is provided in the interconnect layer such that the latter comprises two discontinuous interconnect segments extending along a layer plane and connecting the writing current layer in series. The method comprises: depositing the interconnect layer, writing current layer, second ferromagnetic layer, tunnel barrier layer and first ferromagnetic layer; forming the gap in the interconnect layer; filling the gap with the gap material; and forming the pillar by performing a single etch step until the interconnect layer, acting as a stop layer, is reached.

Abstract: A SOT-MRAM cell, comprising at least one magnetic tunnel junction (MTJ) comprising a tunnel barrier layer between a pinned ferromagnetic layer and a free ferromagnetic layer; a SOT line, extending substantially parallel to the plane of the layers and contacting a first end of said at least one MTJ; at least a first source line connected to one end of the SOT line; at least a first bit line and a second bit line, wherein the SOT-MRAM cell comprises one MTJ, each bit line being connected to the other end of the MTJ; or wherein the SOT-MRAM cell comprises two MTJs, each MTJ being connected to one of the first bit line and second bit line.

Abstract: A magnetic memory (MRAM) cell, comprising: a first layer formed from a substantially electrically conductive material; and a magnetic tunnel junction (MTJ) stack formed over the first layer, wherein the MTJ stack comprises: a ferromagnetic reference layer having an in-plane reference magnetization; a tunnel barrier layer; and a ferromagnetic storage layer between the tunnel barrier layer and the first layer, the storage layer having an in-plane storage magnetization; wherein the MTJ stack comprises an arrangement for providing an in-plane uniaxial anisotropy in the storage layer; wherein said in-plane uniaxial anisotropy makes an angle with the direction of the write current that is between 5° and 90°, and wherein said in-plane uniaxial anisotropy has an energy between 40 and 200 kBT and wherein coercivity is larger than 200 Oe.