Abstract: One embodiment is an apparatus comprising a semiconductor integrated circuit (“IC”) chip comprising at least one active component for implementing an amplifier circuit; and a laminate structure comprising a plurality of metal layers, the laminate structure further comprising a plurality of passive components and transmission line-based structures. The semiconductor IC chip is integrated with the laminate structure such that a top layer of the laminate structure comprises a shield over a top of the semiconductor IC chip and the passive components for limiting electromagnetic coupling of signals generated by the amplifier circuit beyond the laminate structure.

Abstract: One embodiment is an apparatus comprising a semiconductor integrated circuit (“IC”) chip comprising at least one active component for implementing an amplifier circuit; and a laminate structure comprising a plurality of metal layers, the laminate structure further comprising a plurality of passive components and transmission line-based structures. The semiconductor IC chip is integrated with the laminate structure such that a top layer of the laminate structure comprises a shield over a top of the semiconductor IC chip and the passive components for limiting magnetic coupling of signals generated by the amplifier circuit beyond the laminate structure.

Abstract: In one example embodiment, a programmable filter is provided, including a plurality of variable-inductance networks and a plurality of variable-capacitance networks. The programmable filter may be implemented in a classical filter topology, with variable-capacitance networks replacing discrete capacitors and variable-inductance networks replacing discrete inductors. An example variable-inductance network comprises a primary inductor with an intermediate tap, and secondary inductor connected at the intermediate tap, with switches for selecting an inductance.

Abstract: In one example embodiment, a programmable filter is provided, including a plurality of variable-inductance networks and a plurality of variable-capacitance networks. The programmable filter may be implemented in a classical filter topology, with variable-capacitance networks replacing discrete capacitors and variable-inductance networks replacing discrete inductors. An example variable-inductance network comprises a primary inductor with an intermediate tap, and secondary inductor connected at the intermediate tap, with switches for selecting an inductance.

Abstract: Varactor and reference oscillator structures are provided that are particularly suited for integrated circuit fabrication and which provide excellent parameter performance (e.g., monotonicity, linearity, low phase noise and low differential and integral non-linearity) so that they are useful in a variety of wireless communication structures (e.g., cellular telephones).

Abstract: Reference signal generators are provided that automatically adjusts a reference signal's amplitude when that signal is delivered into system loads having unknown capacitances. The amplitude is preferably initiated at a maximum amplitude to insure operation of system elements that require the reference signal. It is subsequently adjusted downward to a controlled reference amplitude which is predetermined to be an amplitude sufficient to sustain proper operation of the system elements but sufficiently reduced to minimize the spurious signals typically generated by fast high-level current transitions. In addition, the reduction to the controlled amplitude reduces the system current drain. The level control is realized in a buffer amplifier so that the amplitude level of an oscillator signal can be set independently to maximize its signal-to-noise performance. Accordingly, requirements for the reference amplitude do not compromise requirements for the amplitude level of the oscillator signal.

Abstract: A direct conversion receiver having a homodyning section fed by a received radio frequency signal having a carrier frequency and reference signal having the carrier frequency; and a filter coupled to the monodyning section. The filter includes a plurality of serially coupled high pass filter stages. The high pass filter section acts as a DC offset correction loop that eliminates the serial effect of many amplifier sections on DC offsets arising within components, while maintaining a sufficiently low cutoff frequency to avoid adversely impacting information integrity at higher frequencies. The high pass filter sections also enable the integration of the needed capacitors, thus minimizing external components and connections. Each filter stage includes an amplifier and a low pass filter coupled in a negative feedback arrangement with the amplifier. Each low pass filter is adapted to have the cutoff frequency thereof switch from an initial high cutoff frequency to a subsequent lower cutoff frequency.

Abstract: A filter having a semiconductor chip and a low pass filter section on the chip. The low pass filter section includes a filter transconductor and a filter capacitor connected to the filter capacitor. The low pass filter section has a cut-off frequency related to the transconductance, gmF, of the filter transconductor and the capacitance of the filter capacitor. A gm control circuit having a control circuit transconductor is provided. The gm control circuit includes a first oscillator for producing a reference frequency. The first oscillator has a portion thereof on the chip and an off-chip capacitor and off-chip resistor. The reference frequency is a function of the capacitance of the off-chip capacitor and the resistance of the off-chip resistor. A second oscillator is on the chip and produces a variable frequency. The second oscillator has an on-chip capacitor.

Abstract: A distributed circuit includes a plurality of pairs of cascode coupled first and second transistors with each transistor having base, emitter, and collector electrodes. The first transistor of each pair is disposed to have a first one of emitter and collector electrodes coupled to a reference potential and the second one of said transistors of each pair is disposed to have the base electrode coupled to a reference potential with the second one the collector and emitter electrodes of the first transistor of each pair being coupled to the emitter electrode of the corresponding second transistor of each pair. The network further includes an input propagation network disposed to successively couple the base electrode of each one of the first transistors of each pair of transistors to an input terminal and an output propagation network disposed to couple the collector electrodes of each one of the second transistors of each one of the pair of transistors to an output terminal of the circuit.

Abstract: A phase shifter network which alternates between structurally dual networks is provided. In particular, the phase shifter has a topography which permits the network to be configured as alternatively T or .pi. networks of low pass and high pass delay circuits in accordance with states of a single control signal fed to the phase shifter.

Abstract: A power divider circuit having an input port and three output ports is described. The circuit includes a first power divider stage having an input port which corresponds to the input of the power divider circuit and a pair of output ports with a first resistor coupled between the pair of output ports of the first stage. The power divider further includes first and second pairs of transmission lines with first ones of said lines of each pair having a first characteristic impedance and second ones of said lines having a second, different characteristic impedance generally equal to half of the characteristic impedance of the first ones of said lines. First ends of each one of the transmission lines of each pair are coupled to a corresponding port of the first power combined stage. Second ends of each of said lines or each pairs are coupled by second and third resistors.