Abstract: The present invention provides a method, apparatus, and system for rapid transition of a charge pump circuit from a low power state to a high power state. The charge pump circuit has at least one pump stage. The at least one pump stage includes at least a first capacitor coupled to a gate of a first switching transistor forming a boot node and at least a second capacitor coupled to an output node of the at least one pump stage. It is determined whether the charge pump circuit is in the low power state or the high power state. If the charge pump circuit is in the low power state, a first predetermined voltage and a second predetermined voltage that are different than the ground voltage level are applied to the boot node and the output node, respectively. If the charge pump circuit is in the high power state, the first predetermined voltage and the second predetermined voltage are removed from the boot node and the output node, respectively.

Abstract: An embodiment of the invention is directed to a method of operating a flash memory, which includes discharging at least one local wordline of an unselected block of flash memory cells during an interval in which a selected set of flash memory cells are being conditioned, such that the at least one local wordline does not develop a charge that is sufficient to corrupt the data stored in the unselected block.

Abstract: A circuit for generating one of a plurality of output voltages. The circuit includes a first conductor coupled to a first supply voltage, a second conductor coupled to a second supply voltage, a charge pump having an input and an output, a multiplexor, a first regulation circuit, and a second regulation circuit. The first regulation circuit is coupled to the first input of the multiplexor and the output of the charge pump. The first regulation circuit is for generating a first regulation voltage in response to the first supply voltage and the output of the charge pump such that the charge pump outputs a first output voltage when the first input of the multiplexor is coupled to the output of the multiplexor. The second regulation circuit is coupled to the second input of the multiplexor and the output of the charge pump.

Abstract: A nonvolatile memory residing on a single substrate is described. The nonvolatile memory includes a memory array having at least a memory cell. The memory cell includes a drain region, a source region, a control gate, and a floating gate. A drain programming voltage generation circuit is coupled to a programming voltage source and the drain region of the memory cell for providing a drain programming voltage to the drain region of the memory cell during programming of the memory cell. A control circuit is coupled to the drain programming voltage generation circuit for causing the drain programming voltage to vary with respect to a programming ability of the memory cell such that the memory cell is programmed to be within a predetermined range of a predetermined threshold voltage with a predetermined gate programming voltage for a predetermined programming time.

Abstract: A detection circuit is described that resides in a nonvolatile memory that includes a memory array and a control circuitry coupled to the memory array for controlling operations of the memory array. The detection circuit is coupled to the control circuitry and receives a power supply for detecting potential level of the power supply and for generating a reset signal to reset the control circuitry until the potential level of the power supply rises above a predetermined level. The detection circuit includes a resistor, a first, a second, and a third transistor. The first transistor has a first end coupled to receive the power supply, a second end coupled to a first node, and a third end coupled to the first node. The second transistor has a first end coupled to the first node, a second end coupled to ground, and a third end coupled to the ground. The first and second transistors function as a voltage divider.