Abstract: A high-endurance, computation-in-memory processor includes a plurality of memory computation modules (MCMs). Each of the MCMs comprise a plurality of memory arrays and a respective module controller to program the plurality of memory arrays to perform mathematical operations on a data set, as well as communicate with other of the MCMs to control a data flow between the MCMs. An inter-module interconnect transports operational data between the MCMs, and communicates with the MCMs to maintain queues storing the operational data during transport between the MCMs. A digital signal processor (DSP) transmits input data to the MCMs and retrieves processed data output by the MCMs.