Abstract: A method and apparatus to produce a net list of gates and Flip-Flops for one algorithm in order to find the best compromise between power consumption, speed and silicon surface by using a two step process. First the algorithm is written for a processor that has no restrictions in terms of number and size of register, core, operations set, memory handler and instructions. The program assembly of this processor fits into a two-dimensional table. To increase speed, the tables are configured to place the program operation in as many columns as possible, and to reduce silicon the tables are configured to place operations in a single column with many rows. The second stage consists of converting this virtual processor with its program tables into an HDL file ready for synthesis.

Abstract: The exchange of frames over a network between devices. Each device comprises a communication circuit connected to a processing unit and comprises addresses, each one being associated with a transmission or reception indicator, a single device comprising a same address associated with a transmission indicator. Each address is associated with a memory containing a frame. A master device periodically transmits transmission indicator addresses. The communication circuit of the device for which the transmitted address is associated with a transmission indicator transmits the frame of the memory to said address and provide the processing unit with an identifier of said address. Each communication circuit of a device for which the transmitted address is associated with a reception indicator writes said frame into the memory at said address and provides the processing unit with an identifier of said address.

Abstract: The exchange of frames over a network between devices. Each device comprises a communication circuit connected to a processing unit and comprises addresses, each one being associated with a transmission or reception indicator, a single device comprising a same address associated with a transmission indicator. Each address is associated with a memory containing a frame. A master device periodically transmits transmission indicator addresses. The communication circuit of the device for which the transmitted address is associated with a transmission indicator transmits the frame of the memory to said address and provide the processing unit with an identifier of said address. Each communication circuit of a device for which the transmitted address is associated with a reception indicator writes said frame into the memory at said address and provides the processing unit with an identifier of said address.

Abstract: The present invention relates to a powering method for elements connected in a two-wire bus type network wherein information frames of predetermined length are transmitted at predetermined times. The method consists of regularly sending on the two-wire bus a power supply pulse between the end of an information frame and the beginning of the next frame.

Abstract: The present invention relates to a method for exchanging information frames over a network between circuits having transmission channels of unified addresses and/or reception channels associated with addresses of transmission channels. It includes the steps of periodically transmitting from a master circuit addresses of transmission channels; receiving each address by each circuit and, when the address corresponds to a transmission channel of the circuit, transmitting the information frame contained in the transmission channel after receiving the next address; receiving each information frame by each circuit and, when the address previously received by the circuit is associated with a reception channel of the circuit, providing the received frame to this reception channel after receiving the next address; and retransmitting from each circuit each first address received and each first information frame received.