Patents by Inventor Marc Gerald DiCicco

Marc Gerald DiCicco has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10491209
    Abstract: Exemplary embodiments are related to switch linearizer. A device may include at least one switch. The device may further include a linearizer coupled to the at least one switch and configured to cancel at least a portion of distortion generated by the at least one switch in an off-state.
    Type: Grant
    Filed: July 17, 2013
    Date of Patent: November 26, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Marc Gerald Dicicco, Xiangdong Zhang, Xinwei Wang
  • Patent number: 9985601
    Abstract: A step attenuator with constant input capacitance and having good performance is disclosed. In an exemplary design, an apparatus includes a step attenuator having a constant input capacitance for different amounts of attenuation. The step attenuator receives an input signal, provides a variable amount of attenuation for the input signal, and provides an output signal. The step attenuator may include a plurality of attenuator sections coupled in series. Each attenuator section may include a plurality of capacitors and may have the constant input capacitance. At least one of the plurality of attenuator sections may be selected or unselected to obtain a selected amount of attenuation for the step attenuator. An attenuator section may provide a predetermined amount of attenuation or a variable amount of attenuation when selected. The apparatus may further include a power detector that receives and determines the power of the output signal from the step attenuator.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: May 29, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Xinwei Wang, Xiangdong Zhang, Marc Gerald Dicicco
  • Patent number: 9467196
    Abstract: A device includes a first circuit path coupled to a first node and a second node, the first circuit path having at least one first varactor circuit configured to receive a first tuning voltage, the first circuit path having a resistor with a selectable value, and a second circuit path coupled to the first node and the second node, the second circuit path having at least one second varactor circuit configured to receive a second tuning voltage, the second circuit path having a capacitor with a selectable value.
    Type: Grant
    Filed: February 5, 2014
    Date of Patent: October 11, 2016
    Assignee: Qualcomm Incorporated
    Inventors: James Francis Imbornone, Xinwei Wang, Marc Gerald Dicicco, Frederic Carrez, Zhenying Luo, Xiangdong Zhang
  • Publication number: 20150222319
    Abstract: A device includes a first circuit path coupled to a first node and a second node, the first circuit path having at least one first varactor circuit configured to receive a first tuning voltage, the first circuit path having a resistor with a selectable value, and a second circuit path coupled to the first node and the second node, the second circuit path having at least one second varactor circuit configured to receive a second tuning voltage, the second circuit path having a capacitor with a selectable value.
    Type: Application
    Filed: February 5, 2014
    Publication date: August 6, 2015
    Applicant: QUALCOMM Incorporated
    Inventors: James Francis Imbornone, Xinwei Wang, Marc Gerald Dicicco, Frederic Carrez, Zhenying Luo, Xiangdong Zhang
  • Publication number: 20150022024
    Abstract: Exemplary embodiments are related to switch linearizer. A device may include at least one switch. The device may further include a linearizer coupled to the at least one switch and configured to cancel at least a portion of distortion generated by the at least one switch in an off-state.
    Type: Application
    Filed: July 17, 2013
    Publication date: January 22, 2015
    Inventors: Marc Gerald Dicicco, Xiangdong Zhang, Xinwei Wang
  • Patent number: 8897727
    Abstract: Power detectors with temperature compensation and having improved accuracy over temperature are disclosed. In an aspect of the disclosure, variations of a power detector gain over temperature is reduced by varying both the gate and drain voltages of MOS transistors within a power detector. In an exemplary design, an apparatus includes at least one MOS transistor, which receives an input signal, detects the power of the input signal based on a power detection gain, and provides an output signal indicative of the power of the input signal. The at least one MOS transistor is applied a variable gate bias voltage and a variable drain bias voltage in order to reduce variations of the power detection gain over temperature. At least one additional MOS transistor may receive a second variable gate bias voltage and provide the variable drain bias voltage for the at least one MOS transistor.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: November 25, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Xinwei Wang, Yongrong Zuo, Xiangdong Zhang, Marc Gerald DiCicco
  • Publication number: 20140266518
    Abstract: A step attenuator with constant input capacitance and having good performance is disclosed. In an exemplary design, an apparatus includes a step attenuator having a constant input capacitance for different amounts of attenuation. The step attenuator receives an input signal, provides a variable amount of attenuation for the input signal, and provides an output signal. The step attenuator may include a plurality of attenuator sections coupled in series. Each attenuator section may include a plurality of capacitors and may have the constant input capacitance. At least one of the plurality of attenuator sections may be selected or unselected to obtain a selected amount of attenuation for the step attenuator. An attenuator section may provide a predetermined amount of attenuation or a variable amount of attenuation when selected. The apparatus may further include a power detector that receives and determines the power of the output signal from the step attenuator.
    Type: Application
    Filed: March 14, 2013
    Publication date: September 18, 2014
    Applicant: QUALCOMM INCORPORATED
    Inventors: Xinwei Wang, Xiangdong Zhang, Marc Gerald Dicicco
  • Publication number: 20130324062
    Abstract: Power detectors with temperature compensation and having improved accuracy over temperature are disclosed. In an aspect of the disclosure, variations of a power detector gain over temperature is reduced by varying both the gate and drain voltages of MOS transistors within a power detector. In an exemplary design, an apparatus includes at least one MOS transistor, which receives an input signal, detects the power of the input signal based on a power detection gain, and provides an output signal indicative of the power of the input signal. The at least one MOS transistor is applied a variable gate bias voltage and a variable drain bias voltage in order to reduce variations of the power detection gain over temperature. At least one additional MOS transistor may receive a second variable gate bias voltage and provide the variable drain bias voltage for the at least one MOS transistor.
    Type: Application
    Filed: March 14, 2013
    Publication date: December 5, 2013
    Applicant: QUALCOMM Incorporated
    Inventors: Xinwei Wang, Yongrong Zuo, Xiangdong Zhang, Marc Gerald DiCicco