Abstract: A protection circuit and method for protecting driven circuitry against voltage peaks in a radio frequency signal, “VRF”, past a predetermined voltage level “Vdetect”. The protection circuit includes an input for receiving the radio frequency signal. The protection circuit also includes at least one amplification stage coupled to the input. The amplification stage is operable to produce an amplified signal based on Vdetect?VRF. The protection circuit further includes a hold circuit operable to determine, from the amplified signal produced by the amplification stage, whether a peak voltage Vpeak of the radio frequency signal exceeds Vdetect. The hold circuit is operable to output a first detection value if Vpeak exceeds Vdetect. The hold circuit is operable to output a second detection value if Vpeak does not exceed Vdetect. The protection circuit also includes a latch circuit operable to latch the detection value outputted by the hold circuit.

Abstract: A phase detection system for providing a phase signal indicative of a phase difference between first and second input signals, with the system including a pair of amplification channels for receiving the input signals, with each channel including a plurality of amplifier stages. The outputs of the two amplification channels are connected to the inputs of a multiplier arrangement, with the arrangement producing an uncompensated phase signal. Compensation circuitry is provided to receive a magnitude signal indicative of the relative magnitudes of the two input signals, with the magnitude signal being used to produce a corrected phase signal indicative of the phase difference between the two input signals.

Abstract: A phase detection system for providing a phase signal indicative of a phase difference between first and second input signals, with the system including a pair of amplification channels for receiving the input signals, with each channel including a plurality of amplifier stages. The outputs of the two amplification channels are connected to the inputs of a multiplier arrangement, with the arrangement producing an uncompensated phase signal. Compensation circuitry is provided to receive a magnitude signal indicative of the relative magnitudes of the two input signals, with the magnitude signal being used to produce a corrected phase signal indicative of the phase difference between the two input signals.

Abstract: A LDD that includes write channels and a distributed output current mirror is provided. The distributed output current mirror includes a current mirror for each of the write channels. For each write channel, if the write channel is enabled, it provides a current to the corresponding current mirror. The outputs of each of the current mirrors are coupled together to provide the output current to the laserdiode.

Abstract: A dual-output current driver includes a pair of output stages that provide output current to various devices such as LEDs and laser diodes. An output-stage selector circuit that includes a differential pair is arranged to activate one of the output stages at a time. A pair of push-pull circuits may be employed to drive the differential pair such that high speed switching is possible. A single-ended to differential conversion circuit controls the push-pull circuits. The selected output stage receives a drive current from a differential pair circuit in a current driver circuit. The current driver circuit includes another pair of push-pull circuits that drive its differential pair circuit, and one or more additional differential circuits that are arranged to activate the push-pull circuits. The various differential pair circuits in the current driver circuit can be arranged to provide phase reversal, or modulation of the drive current in the output stages.

Abstract: An auto-zeroed quantizer that has a unit delay characteristic employs switched capacitor techniques to adjust the input common-mode voltage to a proper common-mode voltage for the quantizer. A feed-forward auto-zero scheme is used to initialize the apparatus during an initialization phase. After the initialization phase, a differential input signal is amplified to provide a differential amplified signal. A positive feedback circuit is subsequently activated to increase the difference in the differential amplified signal until the difference saturates at a logic level. The logic level decision is stored in a memory circuit such as a latch. The unit delay quantizer may be utilized in a converter circuit such as a &Dgr;&Sgr; modulator.

Abstract: An apparatus and method for an improved integrator provides for a regulated common-mode voltage. The improved integrator is arranged as a switched capacitor circuit that includes a differential amplifier. The common-mode input voltage of the differential amplifier is regulated by proper arrangement of the switched capacitor circuit. By regulating the common-mode input voltage, the performance of the differential amplifier is improved. Since the common-mode input voltage is regulated, it is possible to operate the improved integrator at power supply levels below 2V. The improved integrator operates with three single-ended reference signals such that the integrator design is simplified and overall costs are reduced. Capacitor ratios may be adjusted to scale the input common-mode voltage of the differential amplifier. The improved integrator may be arranged as a delayed integrator or a non-delayed integrator by changing the control signals on the switches.