Abstract: A system and method for online payments over the Internet, able to handle several transactions coming from various participants and contributing to a single payment on a merchant's bank account. In many cases, the modifications designed to make a merchant server capable of managing transactions from several participants contributing to a single payment are difficult, even impossible, to carry out since the server's architecture is imposed by the structure of the e-commerce platform used. A server (4), called mirror authorization server, is added and connected to a set typically formed by a customer computer (1), a merchant server (2) and a bank authorization server (3). In particular, the mirror authorization server is used to replace the actual bank authorization server for the purpose of performing certain operations.

Abstract: A system and method for online payments over the Internet, able to handle several transactions coming from various participants and contributing to a single payment on a merchant's bank account. In many cases, the modifications designed to make a merchant server capable of managing transactions from several participants contributing to a single payment are difficult, even impossible, to carry out since the server's architecture is imposed by the structure of the e-commerce platform used. A server (4), called mirror authorization server, is added and connected to a set typically formed by a customer computer (1), a merchant server (2) and a bank authorization server (3). In particular, the mirror authorization server is used to replace the actual bank authorization server for the purpose of performing certain operations.

Abstract: A circuit and method for reading a multiple-level floating-gate memory is provided. The reading is done by a gate bias voltage VP that is equal to the voltage needed to obtain a predetermined reference current Iref in the selected storage transistor. The decoding of the stored data element is done by the decoding of the bias voltage VP. Thus the circuit and method reduces the current flowing through the transistors during the reading and reduces the mean electrical stress undergone during each read operation.

Abstract: The disclosure relates to integrated circuits and, more particularly, to a power-on-reset circuit. The proposed circuit produces an inhibition signal when the power is turned on, this signal being interrupted after the supply voltage Vcc has reached a first threshold (VS1) (VS1). Furthermore, the circuit has means to re-trigger the inhibition signal when the supply voltage drops by a certain value, in doing so even if the supply voltage remains above the first threshold. The reliability of the integrated circuit is improved. The disclosed circuit is particularly applicable to the inhibition of the writing circuit of an EEPROM memory.

Abstract: A floating-gate type memory uses voltages that are low in terms of absolute value with a reliable and compact word selection device. The device is compatible with Flash-EEPROM type memories. An N type well transistor is used as a word selection transistor.

Abstract: An EEPROM is organized in matrix form in word lines and bit lines. Storage cells are placed at the intersections of these lines. The cells include floating gate storage transistors. Groups of cells having separate bit lines but sharing a word line are created. Each group is connected to a group selection transistor. The group selection transistor selectively connects the control gates of the storage transistors to control lines, which provide potentials for enabling programming, erasure or reading of the storage transistors.

Abstract: Disclosed is a charge pump type of negative voltage generator circuit, constructed on a P type substrate and supplying a negative voltage at one output by the pumping of negative charges in n series-connected pumping cells, n being an integer, these pumping cells including P type transistors whose wells are connected to a node to be positively biased. This circuit includes a switching circuit for selectively supplying, at the node, a voltage for biasing of the wells that is greater than or equal to the potential present at the output so long as this potential is greater than a positive reference voltage, and provides a voltage of fixed value for biasing of the wells when the potential present at the output is smaller than the reference voltage. Thus, the appearance of latchup phenomena in the transistors of the pumping cells is prevented.

Abstract: A selector switch circuit comprises an input terminal to receive a positive voltage, an input terminal to receive a negative voltage, a command input terminal to receive a first command logic signal and an output terminal to provide an output voltage. The output is connected selectively to one of the input terminals, the first and second input terminals being connected to the output terminal by means of a first transistor and a second transistor and the circuit comprising control means for the production, as a function of the command signal, of the control voltages applied to the control gates of the transistors for the selective connection of the output terminal to one of the input terminals.

Abstract: A phase generator circuit cyclically produces a first pair of phase signals and a second pair of phase signals, comprising a first circuit to produce a first phase of each pair of phase signals, these first phase signals being non-overlapping and switching over between a voltage 0 and a voltage VCC, and second and third circuits for the production, from the first phase signals, respectively of the second phase of the first pair and the second phase of the second pair of phase signals, these second phase signals being non-overlapping with the first phase signals and switching over between a negative voltage -V and a voltage VCC. The disclosure finds application in the piloting of charge pump type of negative voltage generator circuit.

Abstract: The present invention concerns an electrically programmable memory and a method for writing within this memory. In order to avoid the degradation of information in a memory cell following a number of write cycles in the other cells of the same row, the present invention includes a sequence to be carried out before each write cycle of a word within a row. A systematic reading of all the words of a row by using three different read reference potentials is performed in order to find a cell that gives non-compatibility results between any two of the three read cycles. The words of the row are stored in a register. If a non-compatible result is found, which indicates a degradation of information in the row, a systematic re-write of all the words of the row is carried out.

Abstract: The invention relates to integrated circuit memories and more particularly to non-volatile memories of the EEPROM type. The memory is organized in p-bit words (p>1) with p-read circuits operating in a differential way with respect to a reference line. The memory operates with a balancing phase of the bit line and of the reference line prior to the actual read phase. The reference line is common to the p-read circuits and, for this purpose, a balancing circuit is provided in the read circuits, which acts without shorting the bit line and the reference line. Such circuit includes a follower amplifier in a feedback loop arrangement. The follower amplifier changes the bit line potential in a direction tending to null the output of a differential amplifier used for reading the memory cell state.