Abstract: Devices, systems and methods for clamping output voltages of op-amps while minimizing post-clamping recovery delays are described. A circuit, which controls transitions between two operating modes, may include a first comparator for comparing an output voltage with a clamping voltage and outputting a first mode signal, a second comparator for comparing an input voltage with a reference voltage and outputting a second mode signal. A first logic component may receive the mode signals, perform a logical operation, and output a logic signal. A duplex output, based on a value of the logic signal, may output a track signal and an inversely corresponding hold signal, such track and hold signals being used by an op-amp circuit to configure adjusting blocks used to control transients during mode transitions.

Abstract: Devices, systems and methods for clamping output voltages of op-amps while minimizing post-clamping recovery delays are described. A circuit, which controls transitions between two operating modes, may include a first comparator for comparing an output voltage with a clamping voltage and outputting a first mode signal, a second comparator for comparing an input voltage with a reference voltage and outputting a second mode signal. A first logic component may receive the mode signals, perform a logical operation, and output a logic signal. A duplex output, based on a value of the logic signal, may output a track signal and an inversely corresponding hold signal, such track and hold signals being used by an op-amp circuit to configure adjusting blocks used to control transients during mode transitions.

Abstract: In accordance with an embodiment, an offset-compensated active load includes a pair of transistors having control electrodes connected to their drain electrodes through coupling devices. The control electrodes of the transistors are connected to each other through a plurality of charge storage elements. In accordance with another embodiment, an offset current is generated in response to coupling input terminals of an input stage together. The offset current flows towards an active load which generates an offset voltage in response to the offset current. The offset voltage is stored in the plurality of charge storage devices of the offset-compensated active load.

Abstract: In accordance with an embodiment, an offset-compensated active load includes a pair of transistors having control electrodes connected to their drain electrodes through coupling devices. The control electrodes of the transistors are connected to each other through a plurality of charge storage elements. In accordance with another embodiment, an offset current is generated in response to coupling input terminals of an input stage together. The offset current flows towards an active load which generates an offset voltage in response to the offset current. The offset voltage is stored in the plurality of charge storage devices of the offset-compensated active load.

Abstract: An amplifier (210) includes an input stage (310, 320) and an output stage (330). The input stage (310, 320) has an input for receiving an input signal, and an output. The output stage (330) has an input coupled to the output of the input stage (310, 320), and an output for providing an amplified output signal. The output stage (330) includes a gain stage and a bias circuit. The gain stage has an input forming the input of the output stage, an output for providing the amplified output signal, and a first bias terminal. The bias circuit has a first output terminal coupled to the first bias terminal of the gain stage. During a turn-on period the bias circuit gradually ramps the first bias terminal from a first initial voltage to a first bias voltage.

Abstract: In one embodiment, an amplifier circuit is formed to minimize pop and click noise on the outputs of the amplifier circuit. The amplifier circuit is configured to place an output stage of the amplifier circuit in a high impedance state to minimize the pop and click noise. In another embodiment, the amplifier circuit is configured to couple the inputs of two amplifiers together to minimize the pop and click noise.

Abstract: An amplifier (210) includes an input stage (310, 320) and an output stage (330). The input stage (310, 320) has an input for receiving an input signal, and an output. The output stage (330) has an input coupled to the output of the input stage (310, 320), and an output for providing an amplified output signal. The output stage (330) includes a gain stage and a bias circuit. The gain stage has an input forming the input of the output stage, an output for providing the amplified output signal, and a first bias terminal. The bias circuit has a first output terminal coupled to the first bias terminal of the gain stage. During a turn-on period the bias circuit gradually ramps the first bias terminal from a first initial voltage to a first bias voltage.

Abstract: In one embodiment, an amplifier circuit is formed to minimize pop and click noise on the outputs of the amplifier circuit. The amplifier circuit is configured to place an output stage of the amplifier circuit in a high impedance state to minimize the pop and click noise. In another embodiment, the amplifier circuit is configured to couple the inputs of two amplifiers together to minimize the pop and click noise.

Abstract: In one embodiment, an amplifier circuit is formed to minimize pop and click noise on the outputs of the amplifier circuit. The amplifier circuit is configured to place an output stage of the amplifier circuit in a high impedance state to minimize the pop and click noise. In another embodiment, the amplifier circuit is configured to couple the inputs of two amplifiers together to minimize the pop and click noise.

Abstract: In one embodiment, an amplifier circuit is formed to minimize pop and click noise on the outputs of the amplifier circuit. The amplifier circuit is configured to place an output stage of the amplifier circuit in a high impedance state to minimize the pop and click noise. In another embodiment, the amplifier circuit is configured to couple the inputs of two amplifiers together to minimize the pop and click noise.

Abstract: A read/write head for a magnetic medium magnetic is modified by the addition to it of a parallel-connected resistor and by the measurement of the difference in voltage at the terminals of this unit, on the one hand when the read/write head and the resistor are perfectly connected and, on the other hand, when one of the connections is in an open circuit condition or even in short-circuit condition with respect to ground. Consequently, a measurement is taken, preferably, of the state of connection of the read/write head when it is in read mode and not when it is in write mode. It is shown that far greater reliability in the detection of this type of defect is obtained, in avoiding false alarms.