Abstract: Certain aspects of the present disclosure provide techniques and apparatus for quantized machine learning. A quantized input matrix is accessed at a layer of a neural network, and a first interim value is generated in an accumulator by performing matrix multiplication, using the accumulator, of the quantized input matrix and a quantized weight matrix associated with the layer of the neural network. The first interim value is normalized based at least in part on one or more leading sign bits of the first interim value, and the normalized first interim value is dequantized. A second interim value is generated by applying a rounded right-shift operation to the dequantized normalized first interim value, and activation data is generated by applying an activation function to the second interim value.

Abstract: A device includes a vector register file, a memory, and a processor. The vector register file includes a plurality of vector registers. The memory is configured to store a permutation instruction. The processor is configured to access a periodicity parameter of the permutation instruction. The periodicity parameter indicates a count of a plurality of data sources that contain source data for the permutation instruction. The processor is also configured to execute the permutation instruction to, for each particular element of multiple elements of a first permutation result register of the plurality of vector registers, select a data source of the plurality of data sources based at least in part on the count of the plurality of data sources and populate the particular element based on a value in a corresponding element of the selected data source.

Abstract: A device includes a processor that includes a rotation vector register file, a second vector register file, and multiply-accumulate circuitry (MAC). The rotation vector register file includes a rotation vector register. The rotation vector register file is configured to rotate data in the rotation vector register. The second vector register file includes a source vector register. The MAC is configured to receive first input data from the rotation vector register file and second input data from the source vector register.

Abstract: This application is directed to using a single instruction to initiate a sequence of computational operations related to a neural network. An electronic device receives a single instruction to apply a neural network operation to a set of M-bit elements stored in one or more input vector registers. In response to the single instruction, the electronic device implements the neural network operation on the set of M-bit elements to generate a set of P-bit elements by obtaining the set of M-bit elements from the one or more input vector registers, quantizing each of the set of M-bit elements from M bits to P bits, and packing the set of P-bit elements into an output vector register. P is smaller than M. In some embodiments, the neural network operation is a quantization operation including at least a multiplication with a quantization factor and an addition with a zero point.

Abstract: This application is directed to using a single instruction to initiate a sequence of computational operations related to a neural network activation function. An electronic device receives a single instruction to apply a linear activation operation to a set of first elements stored in one or more input vector registers. In response to the single instruction, the linear activation operation is implemented on the set of first elements to generate a set of output elements. For each first element, the electronic device detects a sign value of the respective first element, selects a respective scalar from one or more scalars based on the sign value, and applies the linear activation operation on the respective first element based on the selected respective scalar and a bias value to generate a respective element of the set of output elements. The electronic device quantizes the set of output elements.

Abstract: A device includes a memory configured to store a fast Fourier transform (FFT) instruction and parameters of the FFT instruction, a read-only memory including a phasor table, and a processor. The processor is configured to execute the FFT instruction to determine, based on the parameters of the FFT instruction, a start value and a step size. The processor is configured to execute the FFT instruction to access the phasor table according to the start value and the step size to obtain a set of twiddle values. The processor is also configured to execute the FFT instruction to compute, for each pair of input values in a set of input data, an output value based on the pair of input values and a twiddle value, of the set of twiddle values, that corresponds to that pair of input values.

Abstract: A device includes a processor and a memory configured to store instructions. The processor is configured to receive a particular instruction from among the instructions and to execute the particular instruction to generate first output data corresponding to a sum of first input data and second input data. The processor is also configured to execute the particular instruction to perform a divide operation on the second input data and to generate second output data corresponding to a difference of the first input data and a result of the divide operation.

Abstract: An overlay system can include a substantially planar overlay base including a top side. The base can define a handle receptacle, for instance at a first end of the base. The handle receptacle can include a handle capture section optionally having a tapered profile. A centrally located elongated guide can extend longitudinally along the top side of the base to guide translational movement of the ultrasound probe holder along a longitudinal axis of the base. A handle can be configured to be attached and detached, by a user, with the handle receptacle of the base. The handle can define a channel optionally having a wedge profile. The wedge profile of the handle can correspond to the tapered profile of the handle receptacle. Engagement of the channel to the capture section of the handle receptacle can attach the handle to the base.

Abstract: An overlay system can include a substantially planar overlay base including a top side. The base can define a handle receptacle, for instance at a first end of the base. The handle receptacle can include a handle capture section optionally having a tapered profile. A centrally located elongated guide can extend longitudinally along the top side of the base to guide translational movement of the ultrasound probe holder along a longitudinal axis of the base. A handle can be configured to be attached and detached, by a user, with the handle receptacle of the base. The handle can define a channel optionally having a wedge profile. The wedge profile of the handle can correspond to the tapered profile of the handle receptacle. Engagement of the channel to the capture section of the handle receptacle can attach the handle to the base.

Abstract: An apparatus includes one or more registers configured to store a vector of input values. The apparatus also includes a coefficient determination unit configured to, responsive to execution by a processor of a single instruction, select a plurality of piecewise analysis coefficients. The plurality of piecewise analysis coefficients includes one or more sets of piecewise analysis coefficients, and each set of piecewise analysis coefficients corresponds to an input value of the vector of input values. The apparatus further includes arithmetic logic circuitry configured to, responsive to the execution of at least the single instruction, determine estimated output values of a function based on the plurality of piecewise analysis coefficients and the vector of input values.

Abstract: An apparatus includes one or more registers configured to store a vector of input values. The apparatus also includes a coefficient determination unit configured to, responsive to execution by a processor of a single instruction, select a plurality of piecewise analysis coefficients. The plurality of piecewise analysis coefficients includes one or more sets of piecewise analysis coefficients, and each set of piecewise analysis coefficients corresponds to an input value of the vector of input values. The apparatus further includes arithmetic logic circuitry configured to, responsive to the execution of at least the single instruction, determine estimated output values of a function based on the plurality of piecewise analysis coefficients and the vector of input values.

Abstract: A housing arrangement of a power electronics device includes one power module or several identical power modules, each module with at least one part connected to a hazardous voltage, the arrangement further including a housing part having room for at least one power module. Each power module includes an enclosure part which essentially surrounds the power module and includes electrically insulating material. All the external connections of the power module are placed on one single wall of the enclosure part. The power modules and the enclosure part of the power modules are arranged such that when the power module is installed to the housing part the power module is electrically insulated from the housing part and external connections of the power module are directed to the front side of the housing part.

Abstract: A housing arrangement of a power electronics device, including one power module or several identical power modules, each module with at least one part connected to a hazardous voltage, the arrangement further including a housing part having room for at least one power module. Each power module includes an enclosure part which essentially surrounds the power module and includes electrically insulating material. All the external connections of the power module are placed on one single wall of the enclosure part. The power modules and the enclosure part of the power modules are arranged such that when the power module is installed to the housing part the power module is electrically insulated from the housing part and external connections of the power module are directed to the front side of the housing part.

Abstract: Methods and an apparatus are provided for interpolation of pixels in a pixel array having rows and columns of pixels. The apparatus includes a shift register array to shift pixel values of the pixel array, the shift register array including two or more shift registers; an interpolation filter array interconnected to the shift register array, the interpolation filter array including one or more interpolation filters; and a controller configured to provide pixel values in columns of the pixel array from the shift register array to respective interpolation filters in a first mode and configured to provide pixel values in rows of the pixel array from the shift register array to respective interpolation filters in a second mode. The controller may be configured to supply vertical sub-pixel values from the shift register array to the interpolation filters to generate diagonal sub-pixel values.

Abstract: A method and apparatus utilizing a prediction guided decimated search motion estimation algorithm are provided. The prediction guided decimated search motion estimation algorithm generates a motion vector used to encode a macroblock in a frame from a video sequence. The algorithm includes generating full-pixel seed vectors, performing a full-pixel search around the generated seed vectors, which is followed by a fractional pixel search. The full-pixel seed vectors generated are a predicted motion vector and a hierarchical motion vector. A fractional pixel search may be conducted around a final motion vector generated by the full-pixel search and may include a half-pixel search and a quarter-pixel search. The prediction guided decimated search motion estimation algorithm can be implemented in both software and hardware. The algorithm is characterized by improved efficiency, scalability, and decreased complexity.

Abstract: Disclosed herein is a heat exchange apparatus, which comprises a hollow blade member having a first fluid inlet and a first fluid outlet and a first fluid passageway for a first fluid that extends between the inlet and the outlet. The blade member is sized and shaped to be located in a second fluid passageway for a second fluid. The blade member is configured to enhance thermal energy transfer between the fluids as they flow along their respective passageways.

Abstract: Methods and an apparatus are provided for interpolation of pixels in a pixel array having rows and columns of pixels. The apparatus includes a shift register array to shift pixel values of the pixel array, the shift register array including two or more shift registers; an interpolation filter array interconnected to the shift register array, the interpolation filter array including one or more interpolation filters; and a controller configured to provide pixel values in columns of the pixel array from the shift register array to respective interpolation filters in a first mode and configured to provide pixel values in rows of the pixel array from the shift register array to respective interpolation filters in a second mode. The controller may be configured to supply vertical sub-pixel values from the shift register array to the interpolation filters to generate diagonal sub-pixel values.

Abstract: A graphical user interface for displaying and interacting with a rendered image of a graphical object on a display device. A color value is stored for each pixel in the display device. Object identification data is stored with each pixel covered by the rendered image wherein the object identification data uniquely identifies a particular one of the graphical objects located at the least one pixel.