Patents by Inventor Marc Holder

Marc Holder has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090319589
    Abstract: Technologies are described herein for using efficient log-linear transformations to reduce the complexity of numerical computations. Efficient transforms can convert between linear fixed point values and log space values in about ten processor cycles per sample. A fractional exponent and an integer exponent may be combined together into a log domain variable representation. Log domain arithmetic operations may be performed on the combined variable as a whole. A fractional exponent representation of log domain numerical values can support automatic bit carries from the fractional exponent into the integer exponent. If an intermediate result of a calculation in the log domain causes the fractional portion of the exponent to exceed one, a bit carry can occur over to the integer component of the exponent. This carry can occur automatically due to the conjoined placement of the integer and fractional components of the exponent in the log domain combined variable.
    Type: Application
    Filed: June 21, 2008
    Publication date: December 24, 2009
    Applicant: MICROSOFT CORPORATION
    Inventors: Marc Holder Kluver, Xiaoqin Sun, Chao He
  • Patent number: 6163324
    Abstract: A method of finding median values from different sets of values includes a step of forming a plurality of bit registers. Each bit register has bit groups corresponding respectively to the different sets of values, and each bit group has bit positions corresponding respectively to different individual ones of the values of the corresponding set. Bits in different bit registers at bit positions corresponding to a particular one of the given values indicate the truth or falsity of different possible relationships between the particular given value and other individual ones of the given values in the same set. The method includes a further step of logically ANDing different combinations of the bit registers to form a plurality of parallel condition registers having bit positions corresponding respectively to different individual ones of the given values of the different sets.
    Type: Grant
    Filed: June 30, 1998
    Date of Patent: December 19, 2000
    Assignee: Microsoft Corporation
    Inventor: Marc Holder