Abstract: A method for determining sensor parameters of an actively-driven sensor system may include performing an initialization operation to establish a baseline estimate of the sensor parameters, obtaining as few as three samples of a measured physical quantity versus frequency for the actively-driven sensor system, performing a refinement operation to provide a refined version of the sensor parameters based on the as few as three samples, iteratively repeating the refinement operation until the difference between successive refined versions of the sensor parameters is below a defined threshold, and outputting the refined sensor parameters as updated sensor parameters for the actively-driven sensor system.

Abstract: A method for determining sensor parameters of an actively-driven sensor system may include performing an initialization operation to establish a baseline estimate of the sensor parameters, obtaining as few as three samples of a measured physical quantity versus frequency for the actively-driven sensor system, performing a refinement operation to provide a refined version of the sensor parameters based on the as few as three samples, iteratively repeating the refinement operation until the difference between successive refined versions of the sensor parameters is below a defined threshold, and outputting the refined sensor parameters as updated sensor parameters for the actively-driven sensor system.

Abstract: A method for generating a not-yet (NYET) signal in a recovered reference system for recovering a device reference clock on a device, wherein the NYET signal indicates that the device is not yet ready for transition into a low power mode, in order to improve a quality of a recovered reference clock representative of a host reference clock of a host communicatively coupled to the device, may be provided. The method may include detecting receipt of start-of-frame markers from the host to the device, responsive to detecting receipt of the markers, determining whether a condition for NYET generation is being met, responsive to the condition for NYET generation being met, generating the NYET signal to cause the host to continue generating the markers, and responsive to the condition for NYET generation not being met, causing the device to generate an acknowledge signal for transition of the device into the low power mode.

Abstract: A device may include an input for receiving information communicated from a host to the device and a controller configured to recover a device reference clock on the device, the device reference clock proportional to a host reference clock of the host, when clock signaling from the host to the device is unavailable. The controller may recover the device reference clock by measuring a ratio between the host reference clock and the device reference clock of the device by monitoring, with the device, host start-of-frame markers communicated from the host to the device via the input, creating a recovered reference clock based on the measured ratio, and creating local start-of-frame markers that are phase locked with the host start-of-frame markers based on the recovered reference clock.

Abstract: A device may include an input for receiving information communicated from a host to the device and a controller configured to recover a device reference clock on the device, the device reference clock proportional to a host reference clock of the host, when clock signaling from the host to the device is unavailable. The controller may recover the device reference clock by measuring a ratio between the host reference clock and the device reference clock of the device by monitoring, with the device, host start-of-frame markers communicated from the host to the device via the input, creating a recovered reference clock based on the measured ratio, and creating local start-of-frame markers that are phase locked with the host start-of-frame markers based on the recovered reference clock.

Abstract: A device may include an input for receiving information communicated from a host to the device and a controller configured to recover a device reference clock on the device, the device reference clock proportional to a host reference clock of the host, when clock signaling from the host to the device is unavailable. The controller may recover the device reference clock by measuring a ratio between the host reference clock and the device reference clock of the device by monitoring, with the device, host start-of-frame markers communicated from the host to the device via the input, creating a recovered reference clock based on the measured ratio, and creating local start-of-frame markers that are phase locked with the host start-of-frame markers based on the recovered reference clock.

Abstract: The system contains a controller unit comprising a memory device, a processing unit, and at least one analog-to-digital converter. A power stage has a plurality of switches, wherein the power stage receives a control signal from the control circuit and a power signal from a power source. The power stage drives two windings of the set of three stator windings to rotate a rotor and maintains one stator winding of the three stator windings undriven. The memory device stores a plurality of values for the driven current and a plurality of demodulated undriven winding voltages. The processing unit compares the plurality of values and periodically calculates a rotor sextant while the rotor rotates. The processing unit compares at least two demodulated undriven winding voltage values corresponding to at least two current values within the rotor sextant to calculate the rotor sextant parity and verify the calculation of the rotor sextant.

Abstract: The system contains a controller unit comprising a memory device, a processing unit, and at least one analog-to-digital converter. A power stage has a plurality of switches, wherein the power stage receives a control signal from the control circuit and a power signal from a power source. The power stage drives two windings of the set of three stator windings to rotate a rotor and maintains one stator winding of the three stator windings undriven. The memory device stores a plurality of values for the driven current and a plurality of demodulated undriven winding voltages. The processing unit compares the plurality of values and periodically calculates a rotor sextant while the rotor rotates. The processing unit compares at least two demodulated undriven winding voltage values corresponding to at least two current values within the rotor sextant to calculate the rotor sextant parity and verify the calculation of the rotor sextant.

Abstract: A linearized controller to operate a switching power converter which includes an inductor having its first terminal coupled to a first voltage (V1) and its second terminal switched so that it alternately connects to a second, higher voltage (V2) or to a common terminal. A sawtooth voltage generator produces a ramp voltage (Vramp) having a period T and an amplitude which varies in response to a control voltage Vx, and a voltage comparator which compares Vramp to a control voltage Vy. The comparator output controls the switching such that T is divided into intervals t1 and t2, during which the second terminal is connected to the common terminal or to V2, respectively. When Vy is maintained in a fixed proportion to V1, V2 is driven to be in the same proportion to Vx, independently of changes in V1, providing a boost converter. A buck converter is similarly realized.

Abstract: A linearized controller to operate a switching power converter which includes an inductor having its first terminal coupled to a first voltage (V1) and its second terminal switched so that it alternately connects to a second, higher voltage (V2) or to a common terminal. A sawtooth voltage generator produces a ramp voltage (Vramp) having a period T and an amplitude which varies in response to a control voltage Vx, and a voltage comparator which compares Vramp to a control voltage Vy. The comparator output controls the switching such that T is divided into intervals t1 and t2, during which the second terminal is connected to the common terminal or to V2, respectively. When Vy is maintained in a fixed proportion to V1, V2 is driven to be in the same proportion to Vx, independently of changes in V1, providing a boost converter. A buck converter is similarly realized.

Abstract: A switching voltage converter, suitably a boost converter, employs an n-type transistor, preferably an NMOS FET, as a series switch, with its drain coupled to the cathode of the converter's diode and its source coupled to the converter's output node. A charge pump driven by the converter's switching voltage provides a voltage Von at the NMOS FET's gate input sufficient to turn the FET on. A series switch controller is arranged to, in response to a control signal, hold the NMOS FET off such that the converter's output voltage Vout is approximately zero regardless of the status of input voltage Vin, or allow the NMOS device to be turned on by Von.

Abstract: A circuit for boosting an input voltage (VIN) to provide a low ripple output voltage (VOUT) regulates flow of current between a source of the input voltage (VIN) and a circuit node (17) in response to a feedback signal (16) representative of the output voltage (VOUT). A charge pump circuit operates to repetitively charge a pump capacitor (CPMP) to a voltage equal to the input voltage (VIN) and redistribute charge between the pump capacitor (CPMP) and a level-shifting capacitor (CLS) coupled between the circuit node (17) and an output conductor (15) conducting the output voltage (VOUT) so as to maintain the boosted output voltage (VOUT).