Abstract: A circuit for clocking includes an input data path, a receiver, a set of flip-flops, at least one interpolator and a controller. The receiver is coupled to the input data path for receiving input data. The flip-flops, coupled to the receiver, sample the input data. A first interpolator, coupled to one or more of the flip-flops, receives the sampled input data. The controller, coupled to the first interpolator, controls the first interpolator by providing phase information regarding the input data to the first interpolator. The circuit reduces any jitter transferred from the input path to an output path.

Abstract: A circuit for clocking includes an input data path, a receiver, a set of flip-flops, at least one interpolator and a controller. The receiver is coupled to the input data path for receiving input data. The flip-flops, coupled to the receiver, sample the input data. A first interpolator, coupled to one or more of the flip-flops, receives the sampled input data. The controller, coupled to the first interpolator, controls the first interpolator by providing phase information regarding the input data to the first interpolator. The circuit reduces any jitter transferred from the input path to an output path.

Abstract: A receiver circuit reduces the need for external clock sources such as crystal oscillators. The receiver circuit makes use of only a single source, the data input, for performing clock and data recovery. A clock and data recovery circuit receives data and at least one reference clock. The clock and data recovery circuit recovers the clock for the input data using the data input and a reference clock. A clean-up phase lock loop circuit reduces jitter in the recovered clock. The recovered clock from the clock and data recovery circuit is input to the clean-up phase lock loop to produce a clean clock. The clean clock is feed into a clock reference circuit. The clock reference circuit generates the reference clock for the clock and data recovery circuit. As such, the reference clock is based on feed back from the recovered clock.

Abstract: A logic circuit employs a shunt peaked technique to enhance the switching speed of the circuit without an increase in power dissipation. A differential logic gate implements a digital circuit function. The shunt peaked logic circuit includes two resistive and two inductive elements. For each differential output line, a resistive element is coupled in series to an inductive element so as to couple the circuit power supply voltage to a differential output line. Under this configuration, the bandwidth of the logic circuit is increased without an increase in power consumption. The logic circuit may be implemented using CML or ECL logic. Techniques for improving large signal performance for active shunt-peaked circuits are also disclosed.

Abstract: A logic circuit employs a shunt peaked technique to enhance the switching speed of the circuit without an increase in power dissipation. A differential logic gate implements a digital circuit function. The shunt peaked logic circuit includes two resistive and two inductive elements. For each differential output line, a resistive element is coupled in series to an inductive element so as to couple the circuit power supply voltage to a differential output line. Under this configuration, the bandwidth of the logic circuit is increased without an increase in power consumption. The logic circuit may be implemented using CML or ECL logic.

Abstract: Problems with source followers employed in active arrays are alleviated by employing a differential amplifier for each element of the active array. However, instead of including an entire differential amplifier within each element, part of the differential amplifier structure is shared among each sensor element connected to a particular column. For example, the differential amplifier may be a differential pair operational transconductance amplifier (OTA) which is connected using a feedback configuration. However, instead of including an OTA within each sensor element of the array, part of the OTA structure is shared among each sensor element connected to a particular column. Although gains greater than one are achievable by employing the differential amplifier with a feedback network, to avoid introducing fixed pattern noise, substantially unity gain is often preferred. Furthermore, the shared differential amplifier model of array reading may be employed for any active array readout application, e.g.

Abstract: A unique hierarchical multiplexer is employed to multiplex signals read out from analog array elements one at a time to an output. In an embodiment of the invention, the multiplexer switching elements, i.e., switches, are arranged in groups in a hierarchical, i.e., tree, configuration. In the tree configuration for a given analog array size, output capacitance is significantly reduced because each analog array element and its associated buffer amplifier drive fewer switches than in other configurations. The lower capacitance reduces any resulting FPN and the resulting lower analog array element and buffer amplifier drive current reduces power dissipation. The reduced capacitance also decreases the transient settling time interval.

Abstract: A loss-of-signal (LOS) detector, for example, for a clock/data recovery (CDR) circuit for an optical fiber communication system, has (1) a transition detector for detecting stuck-on-one and stuck-on-zero LOS conditions and (2) an inconsistency detector for detecting other types of LOS conditions. In one embodiment, the inconsistency detector has two decision circuits having different operating conditions (e.g., different decision thresholds and/or different sampling times). The two decision circuits are configured to generate like output signals (i.e., both high or both low), when a valid input data signal is applied. However, at certain times during certain LOS conditions, the outputs of the two decision circuits will be mutually inconsistent (i.e., one high and one low). If the number of such inconsistencies over a specified time period exceeds a specified threshold level, then an LOS condition is determined.

Abstract: A single slope A/D converter utilizes a sub-nanosecond time digitizer to achieve increased conversion rates independent of a high frequency clock, and so is capable of being implemented in diverse applications. High conversion rates ranging from about 3 MHz to about 12 MHz and higher may be implemented on integrated circuits without using a high frequency clock.

Abstract: An image sensor circuit which employs a photodiode in conjunction with a charge transfer mechanism. By employing the photodiode, at least a portion of the light sensed does not pass through a layer of polysilicon, and so is not prevented from reaching the sensing area by the polysilicon. The image sensor circuit of the invention is made up of device structures readily available in standard CMOS process technologies Advantageously, image sensors embodying the invention show substantially improved quantum efficiency for short wavelength light over the prior art sensors. In addition, image sensors embodying the invention display improved dark current uniformity, thus improving yield.