Abstract: In accordance with an embodiment, a method for operating a successive approximation ADC comprising a first capacitor array includes measuring a first weight of an MSB-ath bit of the ADC by applying a first reference voltage to first terminals of capacitors of the first capacitor array corresponding to the MSB-ath bit, applying a second reference voltage to first terminals of capacitors of the first capacitor array corresponding to significant bits lower than the MSB-ath bit, applying the first reference voltage to first terminals of a first set of capacitors of the first capacitor array corresponding to significant bits higher than the MSB-ath bit, and applying the second reference voltage to first terminals of a second set of capacitors of the first capacitor array corresponding to the significant bits higher than the MSB-ath bit; subsequently, a weight of a capacitance of the capacitors corresponding to the MSB-ath bit is successively approximated.

Abstract: In accordance with an embodiment, a method for operating a successive approximation ADC comprising a first capacitor array includes measuring a first weight of an MSB-ath bit of the ADC by applying a first reference voltage to first terminals of capacitors of the first capacitor array corresponding to the MSB-ath bit, applying a second reference voltage to first terminals of capacitors of the first capacitor array corresponding to significant bits lower than the MSB-ath bit, applying the first reference voltage to first terminals of a first set of capacitors of the first capacitor array corresponding to significant bits higher than the MSB-ath bit, and applying the second reference voltage to first terminals of a second set of capacitors of the first capacitor array corresponding to the significant bits higher than the MSB-ath bit; subsequently, a weight of a capacitance of the capacitors corresponding to the MSB-ath bit is successively approximated.

Abstract: In accordance with an embodiment, a method for operating a successive approximation ADC comprising a first capacitor array includes measuring a first weight of an MSB-ath bit of the ADC by applying a first reference voltage to first terminals of capacitors of the first capacitor array corresponding to the MSB-ath bit, applying a second reference voltage to first terminals of capacitors of the first capacitor array corresponding to significant bits lower than the MSB-ath bit, applying the first reference voltage to first terminals of a first set of capacitors of the first capacitor array corresponding to significant bits higher than the MSB-ath bit, and applying the second reference voltage to first terminals of a second set of capacitors of the first capacitor array corresponding to the significant bits higher than the MSB-ath bit; subsequently, a weight of a capacitance of the capacitors corresponding to the MSB-ath bit is successively approximated.

Abstract: A control system, and corresponding method, for a Multi-Level Hybrid Flying Capacitor (MLHFC) converter. The control system includes a controller configured to control an output of the MLHFC converter; a feedback region detector configured to detect a change in a feedback region of the MLHFC converter; and a controller adjuster configured to, in response to the detected change, adjust the control system to counteract instability.

Abstract: A control system, and corresponding method, for a Multi-Level Hybrid Flying Capacitor (MLHFC) converter. The control system includes a controller configured to control an output of the MLHFC converter; a feedback region detector configured to detect a change in a feedback region of the MLHFC converter; and a controller adjuster configured to, in response to the detected change, adjust the control system to counteract instability.

Abstract: In an example, a device for operating a switching converter is configured to determine a set of perturbed duty cycle values for a converter. A perturbation sequence is superimposed simultaneously onto a duty cycle value for each phase of the converter to form the set of perturbed duty cycle values. The device is further configured to determine an output voltage of the converter that occurs when the converter operates based on the set of perturbed duty cycle values, determine a coefficient vector of system parameters for the converter based on the output voltage and the set of perturbed duty cycle values, and tune a controller based on the coefficient vector. The duty cycle value for each phase of the converter is based on a respective command duty cycle value of a set of command duty cycle values output by the controller.

Abstract: In one example, a circuit for controlling a multi-phase converter is configured to determine an operating condition at a multi-phase converter module. Each phase switching module of a plurality of phase switching modules is configured to electrically couple, based on a respective switching signal, a voltage source to a respective phase of the multi-phase converter module. The circuit is further configured to, for each switching signal, generate an operating value using the operating condition and determine a dynamic hysteresis value for a next switching period using a duration of a previous switching period and a phase shift. The circuit is further configured to, for each switching signal, compare the operating value to a reference value with a hysteretic comparator function using the dynamic hysteresis value and generate the respective switching signal based on the comparison of the operating value to the reference value.

Abstract: In an example, a device for operating a switching converter is configured to receive a composite command duty cycle value. The device is further configured to generate an effective duty cycle value based on a voltage at a switching node. The device is further configured to generate a duty cycle mismatch value using the composite command duty cycle value and the effective duty cycle value so as to generate a plurality of duty cycle mismatch values. Each duty cycle mismatch value of the plurality of duty cycle mismatch values corresponds to a candidate natural frequency value of the converter. The device is further configured to output a candidate natural frequency value of the converter that corresponds to a maximum duty cycle mismatch of the plurality of duty cycle mismatch values.