Abstract: A computer-implemented method for determining a geometric boundary for a mass flow, an energy flow, or a force flow through a channel having a channel wall includes receiving coordinates of edge points of an edge line of a cross-sectional face of the channel, receiving or producing with the edge points, a cross-sectional tiled face with a gap-free and overlap-free arrangement of polygonal flat tiles, the edge points being vertices of tiles of the tiled face, and the edge points and all additional, inner vertices of the tiles, determining additional cross-sectional tiled faces by iteration, varying in the iteration the location of both edge points and inner vertices, terminating the iteration when a predefined termination criterion is met, and outputting information about a smallest cross-sectional face for which, with respect to the tiled faces of the iteration, the total area of all tiles of the tiled face in question is minimized.

Abstract: Disclosed is an image-recorder chip having a multiplicity of image cells provided with field-effect transistors disposed in the form of a two dimensional array and having a readout logic. This present invention is directed to the object of projection of high input signal dynamics onto reduced output signal dynamics, and is distinguished by the arrangement of the light-sensitive element of each image cell being connected between one electrode of a first MOS transistor and gate of a second MOS transistor, and by the other electrode of the first MOS transistor being connected to the one pole of a voltage supply source.

Abstract: A reset circuit in a system comprising a microprocessor coupled to a flash memory by a system bus. The reset circuit has a reset signal generation circuit, a sleep signal generation circuit and a reset override signal generation circuit. The reset signal generation circuit generates a reset signal when power is applied to the flash memory. The reset signal causes the flash memory to enter a predetermined reset state. The sleep signal generation circuit is coupled to the reset signal generation circuit. The sleep signal generation circuit generates a sleep signal. The sleep signal causes the reset signal generation circuit to enter an energy saving sleep mode when the flash memory is placed in the sleep mode. The reset signal causes the sleep signal generation circuit to reset and suppress generation of the sleep signal. The reset override signal generation circuit is coupled to the reset signal generation circuit. The reset override signal is generated during power-up.