Abstract: A disclosed wireless tunneling system tunnels communications between two processing apparatuses through a wireless link, while maintaining compliance of the communications between the two processing apparatuses with at least two different wired communication protocols. In one embodiment, the wireless tunneling system includes two wireless tunneling apparatuses that communicate with each other through the wireless link. A local wireless tunneling apparatus is coupled to a local processing apparatus through a wired connection and a remote wireless tunneling apparatus is coupled to the remote processing apparatus through another wired connection. The two processing apparatuses may communicate with each other through the wireless link using the two wireless tunneling apparatuses as if the two processing apparatuses were connected through wired connections.

Abstract: A microcontroller system includes a higher power reference voltage circuit and a lower power reference voltage circuit configured to draw less power than the higher power reference voltage circuit when enabled. The system includes a power state logic controller configured to enable the lower power reference voltage circuit to provide a first regulated voltage during a power saving mode, and, on exiting the power saving mode, enable the higher power reference voltage circuit to provide a second regulated voltage.

Abstract: A disclosed wireless tunneling system tunnels communications between two processing apparatuses through a wireless link, while maintaining compliance of the communications between the two processing apparatuses with at least two different wired communication protocols. In one embodiment, the wireless tunneling system includes two wireless tunneling apparatuses that communicate with each other through the wireless link. A local wireless tunneling apparatus is coupled to a local processing apparatus through a wired connection and a remote wireless tunneling apparatus is coupled to the remote processing apparatus through another wired connection. The two processing apparatuses may communicate with each other through the wireless link using the two wireless tunneling apparatuses as if the two processing apparatuses were connected through wired connections.

Abstract: A disclosed wireless tunneling system tunnels communications between two processing apparatuses through a wireless link, while maintaining compliance of the communications between the two processing apparatuses with at least two different wired communication protocols. In one embodiment, the wireless tunneling system includes two wireless tunneling apparatuses that communicate with each other through the wireless link. A local wireless tunneling apparatus is coupled to a local processing apparatus through a wired connection and a remote wireless tunneling apparatus is coupled to the remote processing apparatus through another wired connection. The two processing apparatuses may communicate with each other through the wireless link using the two wireless tunneling apparatuses as if the two processing apparatuses were connected through wired connections.

Abstract: A microcontroller system includes a higher power reference voltage circuit and a lower power reference voltage circuit configured to draw less power than the higher power reference voltage circuit when enabled. The system includes a power state logic controller configured to enable the lower power reference voltage circuit to provide a first regulated voltage during a power saving mode, and, on exiting the power saving mode, enable the higher power reference voltage circuit to provide a second regulated voltage.

Abstract: A microcontroller system includes a higher power reference voltage circuit and a lower power reference voltage circuit configured to draw less power than the higher power reference voltage circuit when enabled. The system includes a power state logic controller configured to enable the lower power reference voltage circuit to provide a first regulated voltage during a power saving mode, and, on exiting the power saving mode, enable the higher power reference voltage circuit to provide a second regulated voltage.

Abstract: A disclosed wireless tunneling system tunnels communications between two processing apparatuses through a wireless link, while maintaining compliance of the communications between the two processing apparatuses with at least two different wired communication protocols. In one embodiment, the wireless tunneling system includes two wireless tunneling apparatuses that communicate with each other through the wireless link. A local wireless tunneling apparatus is coupled to a local processing apparatus through a wired connection and a remote wireless tunneling apparatus is coupled to the remote processing apparatus through another wired connection. The two processing apparatuses may communicate with each other through the wireless link using the two wireless tunneling apparatuses as if the two processing apparatuses were connected through wired connections.

Abstract: A device is provided for connecting two hybrid electrical transmission cables each having stranded first conductive wires made of a first metal in the central zone of the cable and second conductive wires that are made of a second metal of higher hardness than that of the first metal and wound on and outside this central zone, the second conductive wires of the cables being connected by an external conductive sleeve. The central first wires of the cables are connected by a weld made of the first metal and connecting their end, this weld and this end being covered by a tube of metal of hardness equal to or higher than that of the second wires, at least partially in line with the sleeve, the end of the second wires being re-formed on the first wires and on the tube under the external conductive sleeve.

Abstract: A device is provided for connecting two hybrid electrical transmission cables each having stranded first conductive wires made of a first metal in the central zone of the cable and second conductive wires that are made of a second metal of higher hardness than that of the first metal and wound on and outside this central zone, the second conductive wires of the cables being connected by an external conductive sleeve. The central first wires of the cables are connected by a weld made of the first metal and connecting their end, this weld and this end being covered by a tube of metal of hardness equal to or higher than that of the second wires, at least partially in line with the sleeve, the end of the second wires being re-formed on the first wires and on the tube under the external conductive sleeve.

Abstract: A microcontroller system includes a higher power reference voltage circuit and a lower power reference voltage circuit configured to draw less power than the higher power reference voltage circuit when enabled. The system includes a power state logic controller configured to enable the lower power reference voltage circuit to provide a first regulated voltage during a power saving mode, and, on exiting the power saving mode, enable the higher power reference voltage circuit to provide a second regulated voltage.

Abstract: Embodiments of integrated circuits for mitigating against electrostatic coupling are described. In an embodiment, first gate dielectrics are respectively located over first active regions. First isolation regions are respectively located between the first active regions. Second gate dielectrics are respectively located over second active regions. Second isolation regions are respectively located between the second active regions. In an embodiment, the first active regions are approximately 20 to 80 percent shorter in height/thickness than the second active regions. In another embodiment, the first isolation regions extend above an uppermost surface of the first gate dielectrics while providing gaps between the first isolation regions and sidewalls of the first active regions for receipt of material used in formation of conductive lines. In yet another embodiment, active area stripes are narrower in width at p-base regions and n-base regions than at cathode regions and anode regions respectively thereof.

Abstract: Method and apparatus for an integrated circuit having memory including thyristor-based memory cells is described. A pair of the thyristor-based memory cells are commonly coupled via a bitline region, where a parasitic bipolar junction transistor is defined therebetween responsive to the bitline region being common. In another implementation, the pair of the thyristor-based memory cells are commonly coupled via the anode region, where a parasitic bipolar junction transistor is defined therebetween responsive to the anode region being common. The common bitline or anode region, respectively, has a locally thinned region to inhibit charge transfer between the pair via the parasitic bipolar junction transistor. Moreover, a method for forming a field-effect transistor on a silicon-on-insulator wafer is described, where charge transfer facilitated by a parasitic bipolar transistor is reduced responsive to an increase in dopants at least proximate to an insulator layer.

Abstract: Disclosed are silane-modified urea derivatives which can be produced by reacting diisocyanates with aminosilanes, hydroxysilanes, or mercaptosilanes. The inventive silane-modified urea derivatives are suitable especially for use as auxiliary rheological agents, preferably as thixotropic agents for silane-crosslinking systems, particularly for single-component and two-component adhesives and sealants, paint, lacquers, and coating while causing substantially no increase in viscosity, not being subject to discoloring, being reactive, and positively influencing mechanics.

Abstract: A system for configuring or testing memory may cycle a memory array while substantially concurrently performing other functional testing. In particular implementations, the system may configure, or cycle, a flash memory using a serial interface and test other functional units using the same serial interface substantially concurrently with cycling the flash memory. In some implementations, cycling the flash memory includes erasing and writing to the flash memory in specific patterns in order to dissipate charge that may have accumulated during a fabrication process.

Abstract: The present invention concerns a system comprising a server, a digital recorder, a memory, an optical disc and a drive. The server may be configured to broadcast a software update through an off air network. The digital recorder may be configured to receive an off air download and download the software update. The memory may be configured to store the software update. The drive may be mounted in the digital recorder. The drive may be configured to write the software update from the memory to a writable optical disc. The digital recorder may be upgraded with the software update from the writable optical disc.

Abstract: Writing to a page of flash memory may include receiving write commands that are substantially independent of an internal architecture of the flash memory. In certain embodiments, two operand flash commands are received at a flash controller from a remote controller. In various implementations, the writing process may further include translating each two-operand write command into architecture-dependent flash commands; executing the architecture-dependent flash commands to fill a page buffer associated with the flash memory; and subsequently transferring contents of the page buffer to the page of flash memory.

Abstract: A process for automatically detecting and configuring with the throughput of a network, in which a device: (a) goes into a listen mode; (b) obtains a triplet of successive transitions in a transmitted signal, the triplet delimiting first and second signal levels, one dominant and the other recessive; (c) measures the duration of each of the first and second levels; (d) as a function of the measured durations, obtains a new throughput configuration by determining values for parameters that define a bit length LBIT; (e) validates the new throughput configuration; (g) if at least one throughput adaptation condition is verified, goes into a normal mode, otherwise obtains a next transition of the signal, which delimits with the last previous transition a new level of the signal, then measures the duration of the new level and reiterates steps (d) to (g) taking account of the new signal level.

Abstract: Disclosed are silane-modified urea derivatives which can be produced by reacting diisocyanates with aminosilanes, hydroxysilanes, or mercaptosilanes. The inventive silane-modified urea derivatives are suitable especially for use as auxiliary rheological agents, preferably as thixotropic agents for silane-crosslinking systems, particularly for single-component and two-component adhesives and sealants, paint, lacquers, and coating while causing substantially no increase in viscosity, not being subject to discoloring, being reactive, and positively influencing mechanics.

Abstract: A system for configuring or testing memory may cycle a memory array while substantially concurrently performing other functional testing. In particular implementations, the system may configure, or cycle, a flash memory using a serial interface and test other functional units using the same serial interface substantially concurrently with cycling the flash memory. In some implementations, cycling the flash memory includes erasing and writing to the flash memory in specific patterns in order to dissipate charge that may have accumulated during a fabrication process.

Abstract: Writing to a page of flash memory may include receiving write commands that are substantially independent of an internal architecture of the flash memory. In certain embodiments, two operand flash commands are received at a flash controller from a remote controller. In various implementations, the writing process may further include translating each two-operand write command into architecture-dependent flash commands; executing the architecture-dependent flash commands to fill a page buffer associated with the flash memory; and subsequently transferring contents of the page buffer to the page of flash memory.