Abstract: Devices under test (DUTs) can be tested in a test system that includes an aligner and test cells. A DUT can be moved into and clamped in an aligned position on a carrier in the aligner. In the align position, electrically conductive terminals of the DUT can be in a predetermined position with respect to carrier alignment features of the carrier. The DUT/carrier combination can then be moved from the aligner into one of the test cells, where alignment features of the carrier are mechanically coupled with alignment features of a contactor in the test cell. The mechanical coupling automatically aligns terminals of the DUT with probes of the contactor. The probes thus contact and make electrical connections with the terminals of the DUT. The DUT is then tested. The aligner and each of the test cells can be separate and independent devices so that a DUT can be aligned in the aligner while other DUTs, having previously been aligned to a carrier in the aligner, are tested in a test cell.

Abstract: Devices under test (DUTs) can be tested in a test system that includes an aligner and test cells. A DUT can be moved into and clamped in an aligned position on a carrier in the aligner. In the align position, electrically conductive terminals of the DUT can be in a predetermined position with respect to carrier alignment features of the carrier. The DUT/carrier combination can then be moved from the aligner into one of the test cells, where alignment features of the carrier are mechanically coupled with alignment features of a contactor in the test cell. The mechanical coupling automatically aligns terminals of the DUT with probes of the contactor. The probes thus contact and make electrical connections with the terminals of the DUT. The DUT is then tested. The aligner and each of the test cells can be separate and independent devices so that a DUT can be aligned in the aligner while other DUTs, having previously been aligned to a carrier in the aligner, are tested in a test cell.

Abstract: A system for testing an integrated circuit device under test (DUT) communicating though synchronous digital signals and through a high speed serialization/de-serialization (serdes) bus includes a serdes interface circuit for communicating with the DUT via the serdes bus and an integrated circuit (IC) tester for communicating with the DUT and with the serdes interface circuit via digital signals. State changes in the digital signals are synchronized to a clock signal within the IC tester. The serdes interface circuit receives instructions from the IC tester via at least one of the digital signals and responds to the instructions by transmitting data to the DUT via the serdes bus using appropriate serdes protocol, by receiving and storing data transmitted by the DUT via the serdes bus, and by thereafter forwarding the stored data to the IC tester via at least one of the digital signals.