Patents by Inventor Marc M. Hoffman
Marc M. Hoffman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9639356Abstract: An example method of updating an output data vector includes identifying a data value vector including element data values. The method also includes identifying an address value vector including a set of elements. The method further includes applying a conditional operator to each element of the set of elements in the address value vector. The method also includes for each element data value in the data value vector, determining whether to update an output data vector based on applying the conditional operator.Type: GrantFiled: March 15, 2013Date of Patent: May 2, 2017Assignee: Qualcomm IncorporatedInventors: Marc M. Hoffman, Ajay Anant Ingle, Jose Fridman
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Patent number: 9639503Abstract: An example method for placing one or more element data values into an output vector includes identifying a vertical permute control vector including a plurality of elements, each element of the plurality of elements including a register address. The method also includes for each element of the plurality of elements, reading a register address from the vertical permute control vector. The method further includes retrieving a plurality of element data values based on the register address. The method also includes identifying a horizontal permute control vector including a set of addresses corresponding to an output vector. The method further includes placing at least some of the retrieved element data values of the plurality of element data values into the output vector based on the set of addresses in the horizontal permute control vector.Type: GrantFiled: March 15, 2013Date of Patent: May 2, 2017Assignee: QUALCOMM IncorporatedInventors: Ajay Anant Ingle, David J. Hoyle, Marc M. Hoffman
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Patent number: 9632781Abstract: Techniques are provided for executing a vector alignment instruction. A scalar register file in a first processor is configured to share one or more register values with a second processor, the one or more register values accessed from the scalar register file according to an Rt address specified in a vector alignment instruction, wherein a start location is determined from one of the shared register values. An alignment circuit in the second processor is configured to align data identified between the start location within a beginning Vu register of a vector register file (VRF) and an end location of a last Vu register of the VRF according to the vector alignment instruction. A store circuit is configured to select the aligned data from the alignment circuit and store the aligned data in the vector register file according to an alignment store address specified by the vector alignment instruction.Type: GrantFiled: February 26, 2013Date of Patent: April 25, 2017Assignee: QUALCOMM IncorporatedInventors: Ajay A. Ingle, Marc M. Hoffman, Jose Fridman, Lucian Codrescu
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Patent number: 9606960Abstract: An example method for placing one or more element data values into an output vector includes identifying a vertical permute control vector including a plurality of elements, each element of the plurality of elements including a register address. The method also includes for each element of the plurality of elements, reading a register address from the vertical permute control vector. The method further includes retrieving a plurality of element data values based on the register address. The method also includes identifying a horizontal permute control vector including a set of addresses corresponding to an output vector. The method further includes placing at least some of the retrieved element data values of the plurality of element data values into the output vector based on the set of addresses in the horizontal permute control vector.Type: GrantFiled: March 15, 2013Date of Patent: March 28, 2017Assignee: QUALCOMM IncorporatedInventors: Ajay Anant Ingle, David J. Hoyle, Marc M. Hoffman
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Patent number: 9342479Abstract: Systems and methods of data extraction in a vector processor are disclosed. In a particular embodiment a method of data extraction in a vector processor includes copying at least one data element to a source register of a permutation network. The method includes reordering multiple data elements of the source register, populating a destination register of the permutation network with the reordered data elements, and copying the reordered data elements from the destination register to a memory.Type: GrantFiled: August 23, 2012Date of Patent: May 17, 2016Assignee: QUALCOMM IncorporatedInventors: Jose Fridman, Ajay Anant Ingle, Deepak Mathew, Marc M. Hoffman, Michael John Lopez
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Patent number: 9268571Abstract: A method includes selectively coupling a first address line of a plurality of address lines and a second address line of the plurality of address lines to a first element bank of a plurality of element banks of a vector register file according to a selection pattern. The method also includes accessing data stored within the first element bank that is selectively addressed by the first address line via a single read port.Type: GrantFiled: October 18, 2012Date of Patent: February 23, 2016Assignee: QUALCOMM IncorporatedInventors: Ajay Anant Ingle, Marc M. Hoffman, Deepak Mathew
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Patent number: 9130786Abstract: An apparatus includes selection logic configured to select a first subset of a first set of samples stored at a first set of registers. The first subset includes a first sample stored at a first register of the first set of registers and further includes a second sample stored at a second register of the first set of registers. The apparatus further includes shift logic configured to shift a second set of samples stored at a second set of registers. The apparatus further includes a channel estimator configured to generate a first value associated with a channel estimate based on the first subset and further based on a second subset of the shifted second set of samples.Type: GrantFiled: March 15, 2013Date of Patent: September 8, 2015Assignee: Qualcomm IncorporatedInventors: Deepak Mathew, Ajay Anant Ingle, Mao Zeng, Marc M. Hoffman
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Publication number: 20140281372Abstract: An example method for placing one or more element data values into an output vector includes identifying a vertical permute control vector including a plurality of elements, each element of the plurality of elements including a register address. The method also includes for each element of the plurality of elements, reading a register address from the vertical permute control vector. The method further includes retrieving a plurality of element data values based on the register address. The method also includes identifying a horizontal permute control vector including a set of addresses corresponding to an output vector. The method further includes placing at least some of the retrieved element data values of the plurality of element data values into the output vector based on the set of addresses in the horizontal permute control vector.Type: ApplicationFiled: March 15, 2013Publication date: September 18, 2014Applicant: QUALCOMM INCORPORATEDInventors: Ajay Anant Ingle, David J. Hoyle, Marc M. Hoffman
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Publication number: 20140270017Abstract: An apparatus includes selection logic configured to select a first subset of a first set of samples stored at a first set of registers. The first subset includes a first sample stored at a first register of the first set of registers and further includes a second sample stored at a second register of the first set of registers. The apparatus further includes shift logic configured to shift a second set of samples stored at a second set of registers. The apparatus further includes a channel estimator configured to generate a first value associated with a channel estimate based on the first subset and further based on a second subset of the shifted second set of samples.Type: ApplicationFiled: March 15, 2013Publication date: September 18, 2014Applicant: QUALCOMM INCORPORATEDInventors: Deepak Mathew, Ajay Anant Ingle, Mao Zeng, Marc M. Hoffman
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Publication number: 20140281421Abstract: An example method of updating an output data vector includes identifying a data value vector including element data values. The method also includes identifying an address value vector including a set of elements. The method further includes applying a conditional operator to each element of the set of elements in the address value vector. The method also includes for each element data value in the data value vector, determining whether to update an output data vector based on applying the conditional operator.Type: ApplicationFiled: March 15, 2013Publication date: September 18, 2014Applicant: QUALCOMM INCORPORATEDInventors: Marc M. Hoffman, Ajay Anant Ingle, Jose Fridman
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Publication number: 20140281368Abstract: An example method for executing multiple instructions in one or more slots includes receiving a packet including multiple instructions and executing the multiple instructions in one or more slots in a time shared manner. Each slot is associated with an execution data path or a memory data path. An example method for executing at least one instruction in a plurality of phases includes receiving a packet including an instruction, splitting the instruction into a plurality of phases, and executing the instruction in the plurality of phases.Type: ApplicationFiled: March 14, 2013Publication date: September 18, 2014Applicant: QUALCOMM INCORPORATEDInventors: Ajay Anant Ingle, Lucian Codrescu, David J. Hoyle, Jose Fridman, Marc M. Hoffman, Deepak Mathew
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Publication number: 20140244967Abstract: Techniques are provided for executing a vector alignment instruction. A scalar register file in a first processor is configured to share one or more register values with a second processor, the one or more register values accessed from the scalar register file according to an Rt address specified, in a vector alignment instruction, wherein a start location is determined from one of the shared register values. An alignment circuit in the second processor is configured to align data identified between the start location within a beginning Vu register of a vector register file (VRF) and an end location of a last Vu register of the VRF according to the vector alignment instruction. A store circuit is configured to select the aligned data from the alignment circuit and store the aligned data in the vector register file according to an alignment store address specified by the vector alignment instruction.Type: ApplicationFiled: February 26, 2013Publication date: August 28, 2014Applicant: Qualcomm IncorporatedInventors: Ajay A. Ingle, Marc M. Hoffman, Jose Fridman, Lucian Codrescu
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Patent number: 8787422Abstract: A method includes executing a first instruction at a processor to perform a first fast Fourier transform (FFT) operation on a set of inputs in a time domain to produce data in a frequency domain, where the set of inputs is in a first order and where the data in the frequency domain is in a second order. The method also includes performing an operation on the data in the frequency domain to produce data in the frequency domain, where the data in the frequency domain is in the second order. The method includes executing a second instruction at the processor to perform a second FFT operation on the data in the frequency domain to produce data in the time domain, where the data in the time domain is in the first order.Type: GrantFiled: December 13, 2011Date of Patent: July 22, 2014Assignee: QUALCOMM IncorporatedInventors: Marc M. Hoffman, Ajay Anant Ingle, Mao Zeng
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Publication number: 20140115227Abstract: A method includes selectively coupling a first address line of a plurality of address lines and a second address line of the plurality of address lines to a first element bank of a plurality of element banks of a vector register file according to a selection pattern. The method also includes accessing data stored within the first element bank that is selectively addressed by the first address line via a single read port.Type: ApplicationFiled: October 18, 2012Publication date: April 24, 2014Applicant: QUALCOMM IncorporatedInventors: Ajay Anant Ingle, Marc M. Hoffman, Deepak Mathew
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Publication number: 20140059323Abstract: Systems and methods of data extraction in a vector processor are disclosed. In a particular embodiment a method of data extraction in a vector processor includes copying at least one data element to a source register of a permutation network. The method includes reordering multiple data elements of the source register, populating a destination register of the permutation network with the reordered data elements, and copying the reordered data elements from the destination register to a memory.Type: ApplicationFiled: August 23, 2012Publication date: February 27, 2014Applicant: Qualcomm IncorporatedInventors: Jose Fridman, Ajay Anant Ingle, Deepak Mathew, Marc M. Hoffman, Michael John Lopez
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Publication number: 20130148694Abstract: A method includes executing a first instruction at a processor to perform a first fast Fourier transform (FFT) operation on a set of inputs in a time domain to produce data in a frequency domain, where the set of inputs is in a first order and where the data in the frequency domain is in a second order. The method also includes performing an operation on the data in the frequency domain to produce data in the frequency domain, where the data in the frequency domain is in the second order. The method includes executing a second instruction at the processor to perform a second FFT operation on the data in the frequency domain to produce data in the time domain, where the data in the time domain is in the first order.Type: ApplicationFiled: December 13, 2011Publication date: June 13, 2013Applicant: QUALCOMM INCORPORATEDInventors: Marc M. Hoffman, Ajay Anant Ingle, Mao Zeng