Abstract: A method of forming a semiconductor package includes providing a carrier, attaching a first surface of a first device on the carrier, wherein the first surface comprises a first active surface of the first device, and attaching a second surface of a second device on the carrier. In one embodiment, the second surface is opposite a third surface of the second semiconductor die and the third surface comprises a second active surface. A first insulating material can be formed between the first device and the second device.

Abstract: Electromagnetic shielding for an integrated circuit packaged device. The method includes forming shielding structures by forming openings in an encapsulated structure. The openings are filled with conductive material that surrounds at least one die. The encapsulated structure may include a plurality of integrated circuit die. A layered redistribution structure is formed on one side of the encapsulated structure.

Abstract: A semiconductor package includes an electrostatic discharge rail capable of being coupled to a first conductive contact and a second conductive contact, a first portion of a voltage triggerable material between the electrostatic discharge rail and the first conductive contact; and a second portion of the voltage triggerable material between the electrostatic discharge rail and the second conductive contact. The first and second conductive contacts may be coupled to the same semiconductor device or different semiconductor devices.

Abstract: A first packaged integrated circuit (IC) includes a package substrate, at least one IC die attached to a first surface of the package substrate, a plurality of conductive members on the first surface at least partially surrounding the at least one IC die and electrically connected to the at least one IC die, an encapsulant over the first surface surrounding the at least one IC die and the plurality of conductive members, wherein at least a portion of each of the plurality of conductive members is exposed by the encapsulant. A second packaged IC may be stacked onto the first packaged IC. The second packaged IC includes at least one IC die and a plurality of conductive members, each conductive member of the plurality of conductive members of the second packaged IC is in contact with a corresponding conductive member of the plurality conductive members of the first packaged IC.

Abstract: A package assembly 200 includes a semiconductor die (e.g., an RF power amplifier) 208 fixed within the cavity of a conductive leadframe 204 using a thermally and electrically-conductive adhesive material 209. The semiconductor die 209 has a first side and a second side, wherein the first side includes at least one active area, and the second side includes at least one contact region. The conductive leadframe (e.g., a copper leadframe) 204 has two planar surfaces and a cavity formed therein. The adhesive material 209 is configured to couple the semiconductor die 208 within the cavity of the conductive leadframe 204 such that the first side of the semiconductor die is substantially coplanar with the first surface of the conductive leadframe.

Abstract: Electromagnetic shielding for an integrated circuit packaged device. The method includes forming shielding structures by forming openings in an encapsulated structure. The openings are filled with conductive material that surrounds at least one die. The encapsulated structure may include a plurality of integrated circuit die. A layered redistribution structure is formed on one side of the encapsulated structure.

Abstract: Forming a packaged device having a semiconductor device having a first major surface and a second major surface includes forming an encapsulating layer over the second major surface of the semiconductor device and around sides of the semiconductor device and leaving the first major surface of the first semiconductor device exposed. A first insulating layer is formed over the first major surface. A plurality of vias are formed in the first insulating layer. A plurality of contacts are formed to the semiconductor device through the first plurality of vias, wherein each of the plurality of contacts has a surface above the first insulating layer. A supporting layer is formed over the first insulating layer leaving an opening over the first plurality of contacts wherein the opening has a sidewall surrounding the plurality of contacts.

Abstract: A device under test (DUT) is tested via a test interposer. The test interposer includes a first set of contacts at a first surface to interface with the contacts of a load board or other interface of an automated test equipment (ATE) and a second set of contacts at an opposing second surface to interface with the contacts of the DUT. The second set of contacts can have a smaller contact pitch than the contact pitch of the first set of contacts to facilitate connection to the smaller pitch of the contacts of the DUT. The test interposer further includes one or more active circuit components or passive circuit components to facilitate testing of the DUT. The test interposer can be implemented as an integrated circuit (IC) package that encapsulates the circuit components.

Abstract: Forming a packaged device having a semiconductor device having a first major surface and a second major surface includes forming an encapsulating layer over the second major surface of the semiconductor device and around sides of the semiconductor device and leaving the first major surface of the first semiconductor device exposed. An insulating layer is formed over the first major surface. A via is formed in the insulating layer. A tangible element is coupled to the semiconductor device through the via. At least a portion of the tangible element is surrounded with a cavity wall having a first face toward the element and a second face away from the element. A supporting layer, after surrounding the tangible element, is formed over the insulating layer so that the supporting layer is adjacent to the second face and blocked from the first face thereby providing protection for the tangible element.

Abstract: A method of forming a semiconductor package includes providing a carrier, attaching a first surface of a first device on the carrier, wherein the first surface comprises a first active surface of the first device, and attaching a second surface of a second device on the carrier. In one embodiment, the second surface is opposite a third surface of the second semiconductor die and the third surface comprises a second active surface. A first insulating material can be formed between the first device and the second device.

Abstract: A method of packaging a first device having a first major surface and a second major surface includes forming a first layer over a second major surface of the first device and around sides of the first device and leaving the first major surface of the first device exposed, wherein the first layer is selected from the group consisting of an encapsulant and a polymer; forming a first dielectric layer over the first major surface of the first device, forming a via in the first dielectric layer, forming a seed layer within the via and over a portion of the first dielectric layer, physically coupling a connector to the seed layer, and plating a conductive material over the seed layer to form a first interconnect in the first via and over a portion of the first dielectric layer.

Abstract: Electromagnetic shielding for an integrated circuit packaged device. The method includes forming shielding structures by forming openings in an encapsulated structure. The openings are filled with conductive material that surrounds at least one die. The encapsulated structure may include a plurality of integrated circuit die. A layered redistribution structure is formed on one side of the encapsulated structure.

Abstract: A first packaged integrated circuit (IC) includes a package substrate, at least one IC die attached to a first surface of the package substrate, a plurality of conductive members on the first surface at least partially surrounding the at least one IC die and electrically connected to the at least one IC die, an encapsulant over the first surface surrounding the at least one IC die and the plurality of conductive members, wherein at least a portion of each of the plurality of conductive members is exposed by the encapsulant. A second packaged IC may be stacked onto the first packaged IC. The second packaged IC includes at least one IC die and a plurality of conductive members, each conductive member of the plurality of conductive members of the second packaged IC is in contact with a corresponding conductive member of the plurality conductive members of the first packaged IC.

Abstract: A device under test (DUT) is tested via a test interposer. The test interposer includes a first set of contacts at a first surface to interface with the contacts of a load board or other interface of an automated test equipment (ATE) and a second set of contacts at an opposing second surface to interface with the contacts of the DUT. The second set of contacts can have a smaller contact pitch than the contact pitch of the first set of contacts to facilitate connection to the smaller pitch of the contacts of the DUT. The test interposer further includes one or more active circuit components or passive circuit components to facilitate testing of the DUT. The test interposer can be implemented as an integrated circuit (IC) package that encapsulates the circuit components.

Abstract: A semiconductor package includes an electrostatic discharge rail capable of being coupled to a first conductive contact and a second conductive contact, a first portion of a voltage triggerable material between the electrostatic discharge rail and the first conductive contact; and a second portion of the voltage triggerable material between the electrostatic discharge rail and the second conductive contact. The first and second conductive contacts may be coupled to the same semiconductor device or different semiconductor devices.

Abstract: A method of packaging a first device having a first major surface and a second major surface includes forming a first layer over a second major surface of the first device and around sides of the first device and leaving the first major surface of the first device exposed, wherein the first layer is selected from the group consisting of an encapsulant and a polymer; forming a first dielectric layer over the first major surface of the first device, forming a via in the first dielectric layer, forming a seed layer within the via and over a portion of the first dielectric layer, physically coupling a connector to the seed layer, and plating a conductive material over the seed layer to form a first interconnect in the first via and over a portion of the first dielectric layer.

Abstract: A method of packaging a first device having a first major surface and a second major surface includes forming a first layer over a second major surface of the first device and around sides of the first device and leaving the first major surface of the first device exposed, wherein the first layer is selected from the group consisting of an encapsulant and a polymer; forming a first dielectric layer over the first major surface of the first device, forming a via in the first dielectric layer, forming a seed layer within the via and over a portion of the first dielectric layer, physically coupling a connector to the seed layer, and plating a conductive material over the seed layer to form a first interconnect in the first via and over a portion of the first dielectric layer.

Abstract: Electromagnetic shielding for an integrated circuit packaged device. The method includes forming shielding structures by forming openings in an encapsulated structure. The openings are filled with conductive material that surrounds at least one die. The encapsulated structure may include a plurality of integrated circuit die. A layered redistribution structure is formed on one side of the encapsulated structure.

Abstract: A method is for packaging a first device having a first major surface and a second major surface. An encapsulant is formed over a second major surface of the first device and around sides of the first device. This leaves the first major surface of the first device exposed. A first dielectric layer is formed over the first major surface of the first device. a side contact interface is formed having at least a portion over the first dielectric layer. The encapsulant is cut to form a plurality of sides of encapsulant. A portion of the encapsulant is removed along a first side of the plurality of sides to expose a portion of the side contact interface along the first side of the plurality of sides.

Abstract: Forming a packaged device having a semiconductor device having a first major surface and a second major surface includes forming an encapsulating layer over the second major surface of the semiconductor device and around sides of the semiconductor device and leaving the first major surface of the first semiconductor device exposed. A first insulating layer is formed over the first major surface. A plurality of vias are formed in the first insulating layer. A plurality of contacts are formed to the semiconductor device through the first plurality of vias, wherein each of the plurality of contacts has a surface above the first insulating layer. A supporting layer is formed over the first insulating layer leaving an opening over the first plurality of contacts wherein the opening has a sidewall surrounding the plurality of contacts.