Patents by Inventor Marc Mantelli

Marc Mantelli has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10796763
    Abstract: A split-gate memory cell includes a state transistor possessing a control gate and a floating gate and a selection transistor possessing a selection gate. The split-gate memory cell is programmed by applying, during a programming duration, a first voltage to the control gate, a second voltage to a drain of the state transistor and a third voltage to the selection gate of the selection transistor. The third voltage is transitioned during the programming duration between a first value and a second value greater than the first value.
    Type: Grant
    Filed: January 24, 2019
    Date of Patent: October 6, 2020
    Assignees: STMicroelectronics (Rousset) SAS, STMicroelectronics (Crolles 2) SAS
    Inventors: Francesco La Rosa, Marc Mantelli, Stephan Niel, Arnaud Regnier
  • Publication number: 20200274722
    Abstract: In accordance with an embodiment, a physically unclonable function device includes a set of transistor pairs, transistors of the set of transistor pairs having a randomly distributed effective threshold voltage belonging to a common random distribution; a differential read circuit configured to measure a threshold difference between the effective threshold voltages of transistors of transistor pairs of the set of transistor pairs, and to identify a transistor pair in which the measured threshold difference is smaller than a margin value as being an unreliable transistor pair; and a write circuit configured to shift the effective threshold voltage of a transistor of the unreliable transistor pair to be inside the common random distribution.
    Type: Application
    Filed: February 6, 2020
    Publication date: August 27, 2020
    Inventors: Francesco La Rosa, Marc Mantelli, Stephan Niel, Arnaud Regnier
  • Publication number: 20190237141
    Abstract: A split-gate memory cell includes a state transistor possessing a control gate and a floating gate and a selection transistor possessing a selection gate. The split-gate memory cell is programmed by applying, during a programming duration, a first voltage to the control gate, a second voltage to a drain of the state transistor and a third voltage to the selection gate of the selection transistor. The third voltage is transitioned during the programming duration between a first value and a second value greater than the first value.
    Type: Application
    Filed: January 24, 2019
    Publication date: August 1, 2019
    Applicants: STMicroelectronics (Rousset) SAS, STMicroelectronics (Crolles 2) SAS
    Inventors: Francesco LA ROSA, Marc MANTELLI, Stephan NIEL, Arnaud REGNIER
  • Patent number: 10192999
    Abstract: Various embodiments provide a memory cell that includes a vertical selection gate, a floating gate extending above the substrate, wherein the floating gate also extends above a portion of the vertical selection gate, over a non-zero overlap distance, the memory cell comprising a doped region implanted at the intersection of a vertical channel region extending opposite the selection gate and a horizontal channel region extending opposite the floating gate.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: January 29, 2019
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Marc Mantelli, Stephan Niel, Arnaud Regnier, Francesco La Rosa, Julien Delalleau
  • Publication number: 20180145183
    Abstract: Various embodiments provide a memory cell that includes a vertical selection gate, a floating gate extending above the substrate, wherein the floating gate also extends above a portion of the vertical selection gate, over a non-zero overlap distance, the memory cell comprising a doped region implanted at the intersection of a vertical channel region extending opposite the selection gate and a horizontal channel region extending opposite the floating gate.
    Type: Application
    Filed: December 22, 2017
    Publication date: May 24, 2018
    Inventors: Marc MANTELLI, Stephan NIEL, Arnaud REGNIER, Francesco LA ROSA, Julien DELALLEAU
  • Patent number: 9876122
    Abstract: Various embodiments provide a memory cell that includes a vertical selection gate, a floating gate extending above the substrate, wherein the floating gate also extends above a portion of the vertical selection gate, over a non-zero overlap distance, the memory cell comprising a doped region implanted at the intersection of a vertical channel region extending opposite the selection gate and a horizontal channel region extending opposite the floating gate.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: January 23, 2018
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Marc Mantelli, Stephan Niel, Arnaud Regnier, Francesco La Rosa, Julien Delalleau
  • Publication number: 20170084749
    Abstract: Various embodiments provide a memory cell that includes a vertical selection gate, a floating gate extending above the substrate, wherein the floating gate also extends above a portion of the vertical selection gate, over a non-zero overlap distance, the memory cell comprising a doped region implanted at the intersection of a vertical channel region extending opposite the selection gate and a horizontal channel region extending opposite the floating gate.
    Type: Application
    Filed: November 30, 2016
    Publication date: March 23, 2017
    Inventors: Marc MANTELLI, Stephan NIEL, Arnaud REGNIER, Francesco LA ROSA, Julien DELALLEAU
  • Patent number: 9543311
    Abstract: Various embodiments provide a memory cell that includes a vertical selection gate, a floating gate extending above the substrate, wherein the floating gate also extends above a portion of the vertical selection gate, over a non-zero overlap distance, the memory cell comprising a doped region implanted at the intersection of a vertical channel region extending opposite the selection gate and a horizontal channel region extending opposite the floating gate.
    Type: Grant
    Filed: February 18, 2015
    Date of Patent: January 10, 2017
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Marc Mantelli, Stephan Niel, Arnaud Regnier, Francesco La Rosa, Julien Delalleau
  • Publication number: 20150236031
    Abstract: The present disclosure relates to a memory cell that includes a vertical selection gate, a floating gate extending above the substrate, wherein the floating gate also extends above a portion of the vertical selection gate, over a non-zero overlap distance, the memory cell comprising a doped region implanted at the intersection of a vertical channel region extending opposite the selection gate and a horizontal channel region extending opposite the floating gate.
    Type: Application
    Filed: February 18, 2015
    Publication date: August 20, 2015
    Inventors: Marc MANTELLI, Stephan NIEL, Arnaud REGNIER, Francesco LA ROSA, Julien DELALLEAU
  • Patent number: 8796765
    Abstract: An integrated circuit chip includes: a plurality of parallel wells of alternated conductivity types formed in the upper portion of a semiconductor substrate of a first conductivity type; in each well of the first type, a plurality of MOS transistors having a channel of the second conductivity type, and in each well of the second type, a plurality of MOS transistors having a channel of the first type, transistors of neighboring wells being inverted-connected; and a device of protection against attacks, including: a layer of the second type extending under said plurality of wells, from the lower surface of said wells; and regions of lateral insulation between the wells, said regions extending from the upper surface of the wells to said layer.
    Type: Grant
    Filed: June 13, 2012
    Date of Patent: August 5, 2014
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Mathieu Lisart, Alexandre Sarafianos, Olivier Gagliano, Marc Mantelli
  • Publication number: 20120320480
    Abstract: An integrated circuit chip includes: a plurality of parallel wells of alternated conductivity types formed in the upper portion of a semiconductor substrate of a first conductivity type; in each well of the first type, a plurality of MOS transistors having a channel of the second conductivity type, and in each well of the second type, a plurality of MOS transistors having a channel of the first type, transistors of neighboring wells being inverted-connected; and a device of protection against attacks, including: a layer of the second type extending under said plurality of wells, from the lower surface of said wells; and regions of lateral insulation between the wells, said regions extending from the upper surface of the wells to said layer.
    Type: Application
    Filed: June 13, 2012
    Publication date: December 20, 2012
    Applicant: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Mathieu Lisart, Alexandre Sarafianos, Olivier Gagliano, Marc Mantelli