Abstract: In a general aspect, a method of writing data in a nonvolatile memory can include performing a first erase or program cycle to write regular data in a first memory cell of the non-volatile memory by (i) applying at least one erase or program pulse to the first memory cell and (ii) determining the state, erased or programmed, of the first memory cell, and repeating (i) and (ii) if the first memory cell is not in the desired state. The method can also include applying a predetermined number of erase or program pulses to write fake data in a second memory cell.

Abstract: The invention relates to a method of programming or erasing memory cells of a nonvolatile memory, including a first erase or program cycle comprising i) applying at least one erase or program pulse to first memory cells, ii) determining the state, erased or programmed, of the memory cells, and repeating steps i) and ii) if the memory cells are not in the desired state, and a second erase or program cycle including applying a predetermined number of erase or program pulses to second memory cells.

Abstract: A power regulation scheme for high voltage output in integrated circuits is realized in a regulated high voltage generator, a voltage clamp, and a power regulator connected between the voltage clamp and the voltage generator. The voltage clamp produces a clamp current during a voltage limiting operation. A regulating clamp current corresponds to an initial limit voltage of the clamp. The power regulator senses the clamp current and suspends voltage generation as the limit magnitude of clamp current is attained. The clamp current is mirrored in a current comparator circuit that triggers a stop signal to the regulated high voltage generator, thus saving power.

Abstract: Techniques for coding and decoding redundant coding for column defects cartography. Defective cell groups identified in a memory array are redundantly encoded with a different bit pattern than the bit pattern used for functional cell groups. The identified defective cell groups are repaired using redundant cell groups in the memory array. The defective cell groups are later re-identified by checking the redundant bit pattern encoded in the cell groups. If new defective cell groups are identified, the memory array is identified as failing. If no new defective cell groups are identified, the memory array is identified as passing, and the identified defective cell groups are repaired.

Abstract: A multi-voltage multiplexer system includes multiple voltage inputs, each voltage input providing a different input voltage, and multiple control inputs operative to select one of the input voltages for output. Each of multiple transistors is connected to a different one of the voltage inputs and to a different one of the control inputs, and the transistors are connected to an output such that the selected input voltage is provided at the output. A bulk of each of the transistors is connected together to form a bulk network, and the bulk network is connected to the gate of each transistor such that the transistors connected to non-selected voltage inputs have gates set at approximately the maximum of the input voltages.

Abstract: A method and system for providing an output voltage greater than a voltage provided by a voltage supply in a semiconductor device are disclosed. The method and system include providing at least one oscillator and at least one voltage storage/discharge stage coupled with the at least one oscillator. The oscillator has a frequency that increases as the voltage decreases. The frequency of the oscillator determines a discharge frequency for the at least one voltage storage/discharge stage.

Abstract: A sense amplifier circuit for low voltage applications is provided. In one implementation, the sense amplifier circuit includes a reference current generation circuit coupled to a power supply. The reference current generation circuit generates a reference current that varies linearly with respect to changes in voltages of the power supply. The sense amplifier circuit further includes a sensing circuit coupled to the reference current generation circuit. The sensing circuit senses an amplitude of a current based at least on part on the reference current.

Abstract: Techniques for coding and decoding redundant coding for column defects cartography. Defective cell groups identified in a memory array are redundantly encoded with a different bit pattern than the bit pattern used for functional cell groups. The identified defective cell groups are repaired using redundant cell groups in the memory array. The defective cell groups are later re-identified by checking the redundant bit pattern encoded in the cell groups. If new defective cell groups are identified, the memory array is identified as failing. If no new defective cell groups are identified, the memory array is identified as passing, and the identified defective cell groups are repaired.

Abstract: A multi-voltage multiplexer system includes multiple voltage inputs, each voltage input providing a different input voltage, and multiple control inputs operative to select one of the input voltages for output. Each of multiple transistors is connected to a different one of the voltage inputs and to a different one of the control inputs, and the transistors are connected to an output such that the selected input voltage is provided at the output. A bulk of each of the transistors is connected together to form a bulk network, and the bulk network is connected to the gate of each transistor such that the transistors connected to non-selected voltage inputs have gates set at approximately the maximum of the input voltages.

Abstract: A sense amplifier circuit for low voltage applications is provided. In one implementation, the sense amplifier circuit includes a reference current generation circuit coupled to a power supply. The reference current generation circuit generates a reference current that varies linearly with respect to changes in voltages of the power supply. The sense amplifier circuit further includes a sensing circuit coupled to the reference current generation circuit. The sensing circuit senses an amplitude of a current based at least on part on the reference current.

Abstract: A method and system for providing an output voltage greater than a voltage provided by a voltage supply in a semiconductor device are disclosed. The method and system include providing at least one oscillator and at least one voltage storage/discharge stage coupled with the at least one oscillator. The oscillator has a frequency that increases as the voltage decreases. The frequency of the oscillator determines a discharge frequency for the at least one voltage storage/discharge stage.

Abstract: A semiconductor oscillator circuit for an EEPROM high voltage charge pump utilizes a current generating means to charge a first and a second capacitor alternatively. The charging current produced by the current generating means is inversely proportional to the ambient temperature. The charging current is proportional to the supply voltage and consequently, the oscillator frequency output remains constant over a variable voltage supply. Such a constant frequency characteristic makes a low voltage operation possible, but slows down the oscillator frequency as temperature increases. The slowing of oscillator frequency limits the charge pump output voltage and enhances the lifespan of the EEPROM cells.

Abstract: Program column latch circuitry of nonvolatile memory is provided with read-back capability to verify that data bits have been correctly loaded into the latch circuits and written to the memory cells. The interface between the low voltage latches and the external input and output data paths is provided with opposite-facing tri-state buffers that allow latched data to be read out for comparison and verification. Writing of latched data to memory cells can be verified by the read-back without needing any external RAM.

Abstract: A power regulation scheme for high voltage output in integrated circuits is realized in a regulated high voltage generator, a voltage clamp, and a power regulator connected between the voltage clamp and the voltage generator. The voltage clamp produces a clamp current during a voltage limiting operation. A regulating clamp current corresponds to an initial limit voltage of the clamp. The power regulator senses the clamp current and suspends voltage generation as the limit magnitude of clamp current is attained. The clamp current is mirrored in a current comparator circuit that triggers a stop signal to the regulated high voltage generator, thus saving power.

Abstract: Program column latch circuitry of nonvolatile memory is provided with read-back capability to verify that data bits have been correctly loaded into the latch circuits and written to the memory cells. The interface between the low voltage latches and the external input and output data paths is provided with opposite-facing tri-state buffers that allow latched data to be read out for comparison and verification. Writing of latched data to memory cells can be verified by the read-back without needing any external RAM.

Abstract: A semiconductor oscillator circuit for an EEPROM high voltage charge pump utilizes a current generating means to charge a first and a second capacitor alternatively. The charging current produced by the current generating means is inversely proportional to the ambient temperature. The charging current is proportional to the supply voltage and consequently, the oscillator frequency output remains constant over a variable voltage supply. Such a constant frequency characteristic makes a low voltage operation possible, but slows down the oscillator frequency as temperature increases. The slowing of oscillator frequency limits the charge pump output voltage and enhances the lifespan of the EEPROM cells.

Abstract: An EEPROM memory circuit in which the loading of the column latches can be performed simultaneously with reading of the memory array. In this memory circuit, the data input connects directly to the column latches, leaving the bit lines open for memory reading by the sense amplifiers, which is connected directly to the bit lines. Two separate Y address decoders, one feeding into the column latches and the other into the bit line select circuit, provide column latch and bit line selection respectively.