Abstract: In some embodiments disclosed herein, the execution of a software program by processor can be simulated using two models of the processor: one “detailed” model that offers a relatively high level of detail and operates relatively slowly; and another “fast” model that offers a relatively low level of detail and operates relatively quickly. Portions of the software program are simulated as being executed on one model or the other according to simulation selection information (e.g., user input). State information is passed between models as the system switches from one model to another. The detailed model can comprise, for example, a “full functional” processor model, while the fast model can comprise, for example, an instruction set simulator (ISS) and a bus cycle engine (BCE). Further embodiments allow a plurality of software programs to be simulated in batch using the disclosed technologies.

Abstract: A simulation of an execution of a software program in an electronic circuit design can be analyzed to determine values simulated as being stored, such as in the memory and registers of the design, including values that are not necessarily observable on the outputs of the design. In some embodiments, a user can indicate a time period in the simulation results, or a portion of the software executable. One or more values stored in the design can be determined according to the circuit design, a description of one or more transactions of values stored in the circuit design, and one or more indications of signals provided on the outputs of the design. This can allow a user to examine values simulated as being stored in the circuit design using, for example, a software debugger showing register and memory watches. The disclosed technologies can be used with various user interface elements.

Abstract: One or more technologies described herein can be used for viewing results of a simulation of a software executable in a multi-processor electronic circuit design. A debug environment can display simulation results related to the multiple processors, for example, as a correlated software debug view of the processors. In at least some embodiments, the disclosed technologies can be used to examine a correlation between an error in the design which is shown in the simulation results and one or more inter-processor synchronization events.