Patents by Inventor Marc P. C. Fossorier

Marc P. C. Fossorier has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7373585
    Abstract: A method generates a combined-replica group-shuffled iterative decoder. First, an error-correcting code and an iterative decoder for an error-correcting code is received. Multiple group-shuffled sub-decoders for the error-correcting code are constructed, based on the iterative decoder. Then, the multiple group-shuffled sub-decoders are combined into a combined-replica group-shuffled iterative decoder.
    Type: Grant
    Filed: January 14, 2005
    Date of Patent: May 13, 2008
    Assignee: Mitsubishi Electric Research Laboratories, Inc.
    Inventors: Jonathan S. Yedidia, Marc P. C. Fossorier, Juntan Zhang, Yige Wang
  • Patent number: 7103825
    Abstract: A method decodes a received word for a binary linear block code based on a finite geometry. First, a parity check matrix representation of the code is defined. The received word is stored in a channel register. An active register represents a current state of the decoder. Each element in the active register can take three states, representing the two possible states of the corresponding bit in the word, and a third state representing uncertainty. Votes from parity checks to elements of the active register are determined from parity checks in the matrix, and the current state of the active register. A recommendation and strength of recommendation for each element in the active register is determined from the votes. The elements in the active register are then updated by comparing the recommendation and strength of recommendation with two thresholds, and the state of the corresponding bit in the received word. When termination conditions are satisfied, the decoder outputs the state of the active register.
    Type: Grant
    Filed: August 19, 2003
    Date of Patent: September 5, 2006
    Assignee: Mitsubishi Electric Research Laboratories, Inc.
    Inventors: Jonathan S. Yedidia, Marc P. C. Fossorier, Ravi Palanki
  • Patent number: 5781569
    Abstract: A differential trellis decoding method for convolutional codes is provided which eliminates from candidacy half of the transitions in each round that it is used, thereby obviating the need for weight calculations for the eliminated transitions. The method is based on a decomposition of the code trellis into fully connected bipartite graphs and the observation that the symmetry of the bipartite graphs of the trellis permits the comparison and selection process for one state to influence the comparison and selection process for other states in the bipartite graph. This method results in a reduced number of operations and hence a reduced complexity for convolutional decoding.
    Type: Grant
    Filed: October 28, 1996
    Date of Patent: July 14, 1998
    Assignee: LSI Logic Corporation
    Inventors: Marc P. C. Fossorier, Shu Lin, Dojun Rhee