Patents by Inventor Marc Péralte Dandin

Marc Péralte Dandin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SYSTEM AND METHOD TO MEASURE CAR-T CELL QUALITY
    Publication number: 20230366873
    Abstract: A system and method utilize capacitance sensor data to identify cell events with single-cell resolution. The method identifies patterns in the sensor data related to events such as mitosis, migration-in to the sensor field, and migration-out. The system may include a processor co-located with the sensor to perform the pattern recognition. Further, microfluidic channels can be provided to direct cells to the sensors.
    Type: Application
    Filed: May 11, 2023
    Publication date: November 16, 2023
    Applicant: Carnegie Mellon University
    Inventors: Marc Peralte Dandin, Ching-Yi Lin
  • Delay circuit with dual delay resolution regime
    Patent number: 10594306
    Abstract: A delay circuit is provided. The delay circuit includes a first regulator and a second regulator, each of which is independently selectable based on a selection signal applied to a selection terminal of the delay circuit. Furthermore, the delay circuit is configurable in one of two distinct delay resolution regimes, each corresponding to only one edge an input signal being actively delayed by the delay circuit when one of the first regulator and the second regulator is enabled and the other one of the first regulator and the second regulator is turned off.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: March 17, 2020
    Assignee: KISKEYA MICROSYSTEMS LLC
    Inventor: Marc Péralte Dandin
  • DELAY CIRCUIT WITH DUAL DELAY RESOLUTION REGIME
    Publication number: 20170230037
    Abstract: A delay circuit is provided. The delay circuit includes a first regulator and a second regulator, each of which is independently selectable based on a selection signal applied to a selection terminal of the delay circuit. Furthermore, the delay circuit is configurable in one of two distinct delay resolution regimes, each corresponding to only one edge an input signal being actively delayed by the delay circuit when one of the first regulator and the second regulator is enabled and the other one of the first regulator and the second regulator is turned off.
    Type: Application
    Filed: April 25, 2017
    Publication date: August 10, 2017
    Applicant: KISKEYA MICROSYSTEMS LLC
    Inventor: Marc Péralte Dandin
  • Single-photon avalanche diode circuit with variable hold-off time and dual delay regime
    Patent number: 9671284
    Abstract: A circuit is provided. The circuit includes a single-photon avalanche diode. The circuit further includes a delay element comprising a first regulator and a second regulator, each of which is independently selectable based on a selection signal applied to a selection terminal of the delay element. The delay element is configured to receive, at an inverting section, an event signal indicative of an avalanche event in the single-photon avalanche diode. Furthermore, the delay element is configurable in one of two distinct delay resolution regimes, each corresponding to only one edge of the event signal being actively delayed by the delay element when one of the first regulator and the second regulator is enabled and the other one of the first regulator and the second regulator is turned off.
    Type: Grant
    Filed: January 17, 2017
    Date of Patent: June 6, 2017
    Assignee: KISKEYA MICROSYSTEMS LLC
    Inventor: Marc Péralte Dandin