Patents by Inventor Marc P. Vertes

Marc P. Vertes has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8984513
    Abstract: A mechanism for replicating programs executing on a computer system having a first storage means is provided. The mechanism identifies the events corresponding to requests from one executing program, which may be different from the executing program to be replicated, which are non-deterministic and identifies the ‘Non Abortable Events’ (NAE's), which change irremediably the state of the external world that need to be reproduced in the replay of the programs. These events are immediately transferred for replay and the executing program is blocked until the transfer is acknowledged. For the other non-deterministic events, they are logged and sent to the executing program, the executing programs remaining blocked only if the log is full and/or if a timer between two NAEs expires, in this case a log transfer to the standby machine is performed to prepare replication before unblocking of the executing program.
    Type: Grant
    Filed: March 30, 2007
    Date of Patent: March 17, 2015
    Assignee: International Business Machines Corporation
    Inventors: Philippe Bergheaud, Dinesh K. Subhraveti, Marc P. Vertes
  • Patent number: 7774647
    Abstract: This invention relates to a transparent and non-intrusive method for monitoring and managing the running of tasks executed in one or more computer processors, in particular in multi-processor systems with a parallel architecture. It proposes a system and method for managing a computer task, termed target, during a given execution period, termed activity period (SchJ, SchR), within a computer system, in a computer processor provided with means of monitoring or estimating performance and including a counter (PMC) with a given possible error in plus or minus, termed relative error, this process comprising on the one hand, an evaluation of a number of executed instructions (NR, NJ) up to at least one given point of said activity period, using said counter; and on the other hand, a generation of data, termed signature (SGJ, SGR), read or calculated from the state of the processor or computer system and corresponding to at least one given point of said activity period.
    Type: Grant
    Filed: January 24, 2006
    Date of Patent: August 10, 2010
    Assignee: International Business Machines Corporation
    Inventor: Marc P. Vertes
  • Publication number: 20090328044
    Abstract: A mechanism for replicating programs executing on a computer system having a first storage means is provided. The mechanism identifies the events corresponding to requests from one executing program, which may be different from the executing program to be replicated, which are non-deterministic and identifies the ‘Non Abortable Events’ (NAE's), which change irremediably the state of the external world that need to be reproduced in the replay of the programs. These events are immediately transferred for replay and the executing program is blocked until the transfer is acknowledged. For the other non-deterministic events, they are logged and sent to the executing program, the executing programs remaining blocked only if the log is full and/or if a timer between two NAEs expires, in this case a log transfer to the standby machine is performed to prepare replication before unblocking of the executing program.
    Type: Application
    Filed: March 30, 2007
    Publication date: December 31, 2009
    Applicant: International Business Machines Corporation
    Inventors: Philippe Bergheaud, Dinesh K. Subhraveti, Marc P. Vertes
  • Publication number: 20090119549
    Abstract: This invention relates to a transparent and non-intrusive method for monitoring and managing the running of tasks executed in one or more computer processors, in particular in multi-processor systems with a parallel architecture. It proposes a system and method for managing a computer task, termed target, during a given execution period, termed activity period (SchJ, SchR), within a computer system, in a computer processor provided with means of monitoring or estimating performance and including a counter (PMC) with a given possible error in plus or minus, termed relative error, this process comprising on the one hand, an evaluation of a number of executed instructions (NR, NJ) up to at least one given point of said activity period, using said counter; and on the other hand, a generation of data, termed signature (SGJ, SGR), read or calculated from the state of the processor or computer system and corresponding to at least one given point of said activity period.
    Type: Application
    Filed: January 24, 2006
    Publication date: May 7, 2009
    Inventor: Marc P. Vertes