Patents by Inventor Marc Probst
Marc Probst has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220231125Abstract: A power semiconductor device includes a control cell for controlling a load current and electrically connected to a load terminal structure on one side and to a drift region on another side. The drift region includes dopants of a first conductivity type. The control cell includes: a mesa extending along a vertical direction and including a contact region having dopants of the first or second conductivity type and electrically connected to the load terminal structure, and a channel region coupled to the drift region; a control electrode configured to control a conduction channel in the channel region; and a contact plug including at least one of a doped semiconductive material or metal, and arranged in contact with the contact region. An electrical connection between the contact region and load terminal structure is established by the contact plug, a portion of which horizontally projects beyond lateral boundaries of the mesa.Type: ApplicationFiled: April 8, 2022Publication date: July 21, 2022Inventors: Hans-Juergen Thees, Stefan Loesch, Marc Probst, Tom Richter, Olaf Storbeck
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Patent number: 11322587Abstract: A power semiconductor device includes a control cell for controlling a load current. The control cell is electrically connected to a load terminal structure on one side and to a drift region on another side. The drift region includes dopants of a first conductivity type. The control cell includes: a mesa extending along a vertical direction and including: a contact region having dopants of the first conductivity type or of a second conductivity type and electrically connected to the load terminal structure, and a channel region coupled to the drift region; a control electrode configured to induce a conduction channel in the channel region; and a contact plug including a doped semiconductive material and arranged in contact with the contact region. An electrical connection between the contact region and load terminal structure is established by the contact plug, a portion of which projects beyond lateral boundaries of the mesa.Type: GrantFiled: June 13, 2020Date of Patent: May 3, 2022Assignee: Infineon Technologies Dresden GmbH & Co. KGInventors: Hans-Juergen Thees, Stefan Loesch, Marc Probst, Tom Richter, Olaf Storbeck
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Publication number: 20200395443Abstract: A power semiconductor device includes a control cell for controlling a load current. The control cell is electrically connected to a load terminal structure on one side and to a drift region on another side. The drift region includes dopants of a first conductivity type. The control cell includes: a mesa extending along a vertical direction and including: a contact region having dopants of the first conductivity type or of a second conductivity type and electrically connected to the load terminal structure, and a channel region coupled to the drift region; a control electrode configured to induce a conduction channel in the channel region; and a contact plug including a doped semiconductive material and arranged in contact with the contact region. An electrical connection between the contact region and load terminal structure is established by the contact plug, a portion of which projects beyond lateral boundaries of the mesa.Type: ApplicationFiled: June 13, 2020Publication date: December 17, 2020Inventors: Hans-Juergen Thees, Stefan Loesch, Marc Probst, Tom Richter, Olaf Storbeck
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Patent number: 10748807Abstract: A semiconductor device includes a semiconductor body having a main surface and a rear surface opposite the main surface, and a trench that extends from the main surface of the semiconductor body towards the rear surface, the trench having an upper trench portion and a lower trench portion, the trench having a width measured along a plane parallel to the main surface. The upper trench portion includes curved sidewalls that that bow outward from a bottom of the upper trench portion. The lower trench portion includes generally planar sidewalls that extend from bottom of the upper trench portion at a first depth into the semiconductor body along the first direction to a contact region. An electrically conductive contact electrode is within the trench, is electrically insulated from the semiconductor body along sidewalls of the trench, and electrically connects to the semiconductor body at a bottom of the trench.Type: GrantFiled: March 6, 2019Date of Patent: August 18, 2020Assignee: Infineon Technologies AGInventors: Torsten Helm, Marc Probst, Uwe Rudolph
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Publication number: 20190198380Abstract: A semiconductor device includes a semiconductor body having a main surface and a rear surface opposite the main surface, and a trench that extends from the main surface of the semiconductor body towards the rear surface, the trench having an upper trench portion and a lower trench portion, the trench having a width measured along a plane parallel to the main surface. The upper trench portion includes curved sidewalls that that bow outward from a bottom of the upper trench portion. The lower trench portion includes generally planar sidewalls that extend from bottom of the upper trench portion at a first depth into the semiconductor body along the first direction to a contact region. An electrically conductive contact electrode is within the trench, is electrically insulated from the semiconductor body along sidewalls of the trench, and electrically connects to the semiconductor body at a bottom of the trench.Type: ApplicationFiled: March 6, 2019Publication date: June 27, 2019Inventors: Torsten Helm, Marc Probst, Uwe Rudolph
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Patent number: 10312159Abstract: A method comprises providing a substrate of a first conductive type and a layer stack arranged on the substrate. The layer stack comprises a first isolation layer, a sacrificial layer, and a second isolation layer. The layer stack comprises a window formed in the layer stack through the second isolation layer, the sacrificial layer and the first isolation layer up to a surface region of the substrate. The method comprises providing a collector layer. The method comprises providing a base layer on the collector layer within the window of the layer stack. The method comprises providing an emitter layer or an emitter layer stack comprising the emitter layer on the base layer within the window of the layer stack. The method further comprises selectively removing the emitter layer or the emitter layer stack at least up to the second isolation layer.Type: GrantFiled: October 31, 2017Date of Patent: June 4, 2019Assignee: Infineon Technologies AGInventors: Frank Hoffmann, Dirk Manger, Andreas Pribil, Marc Probst, Stefan Tegen
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Patent number: 10262889Abstract: An integrated circuit includes a first trench disposed in a semiconductor material, wherein a width of the first trench in an upper portion of the first trench adjacent to a surface of the semiconductor material is smaller than a width of the first trench in a lower portion of the first trench, the lower portion being disposed within the semiconductor material, each width being measured in a plane parallel to a surface of the semiconductor material, each width denoting a distance between inner faces of remaining semiconductor material portions or between outer faces of a filling disposed in the first trench, or between an inner face of a remaining semiconductor material portion and an outer face of a filling disposed in the first trench.Type: GrantFiled: May 23, 2017Date of Patent: April 16, 2019Assignee: Infineon Technologies AGInventors: Torsten Helm, Marc Probst, Uwe Rudolph
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Publication number: 20180166338Abstract: A method comprises providing a substrate of a first conductive type and a layer stack arranged on the substrate. The layer stack comprises a first isolation layer, a sacrificial layer, and a second isolation layer. The layer stack comprises a window formed in the layer stack through the second isolation layer, the sacrificial layer and the first isolation layer up to a surface region of the substrate. The method comprises providing a collector layer. The method comprises providing a base layer on the collector layer within the window of the layer stack. The method comprises providing an emitter layer or an emitter layer stack comprising the emitter layer on the base layer within the window of the layer stack. The method further comprises selectively removing the emitter layer or the emitter layer stack at least up to the second isolation layer.Type: ApplicationFiled: October 31, 2017Publication date: June 14, 2018Inventors: Frank HOFFMANN, Dirk MANGER, Andreas PRIBIL, Marc PROBST, Stefan TEGEN
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Patent number: 9812369Abstract: A method comprises providing a substrate of a first conductive type and a layer stack arranged on the substrate. The layer stack comprises a first isolation layer, a sacrificial layer, and a second isolation layer. The layer stack comprises a window formed in the layer stack through the second isolation layer, the sacrificial layer and the first isolation layer up to a surface region of the substrate. The method comprises providing a collector layer. The method comprises providing a base layer on the collector layer within the window of the layer stack. The method comprises providing an emitter layer or an emitter layer stack comprising the emitter layer on the base layer within the window of the layer stack. The method further comprises selectively removing the emitter layer or the emitter layer stack at least up to the second isolation layer.Type: GrantFiled: March 29, 2016Date of Patent: November 7, 2017Assignee: Infineon Technologies AGInventors: Frank Hoffmann, Dirk Manger, Andreas Pribil, Marc Probst, Stefan Tegen
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Publication number: 20170256437Abstract: An integrated circuit includes a first trench disposed in a semiconductor material, wherein a width of the first trench in an upper portion of the first trench adjacent to a surface of the semiconductor material is smaller than a width of the first trench in a lower portion of the first trench, the lower portion being disposed within the semiconductor material, each width being measured in a plane parallel to a surface of the semiconductor material, each width denoting a distance between inner faces of remaining semiconductor material portions or between outer faces of a filling disposed in the first trench, or between an inner face of a remaining semiconductor material portion and an outer face of a filling disposed in the first trench.Type: ApplicationFiled: May 23, 2017Publication date: September 7, 2017Inventors: Torstern Helm, Marc Probst, Uwe Rudolph
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Publication number: 20160322257Abstract: A method comprises providing a substrate of a first conductive type and a layer stack arranged on the substrate. The layer stack comprises a first isolation layer, a sacrificial layer, and a second isolation layer. The layer stack comprises a window formed in the layer stack through the second isolation layer, the sacrificial layer and the first isolation layer up to a surface region of the substrate. The method comprises providing a collector layer. The method comprises providing a base layer on the collector layer within the window of the layer stack. The method comprises providing an emitter layer or an emitter layer stack comprising the emitter layer on the base layer within the window of the layer stack. The method further comprises selectively removing the emitter layer or the emitter layer stack at least up to the second isolation layer.Type: ApplicationFiled: March 29, 2016Publication date: November 3, 2016Inventors: Frank HOFFMANN, Dirk MANGER, Andreas PRIBIL, Marc PROBST, Stefan TEGEN
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Publication number: 20150203350Abstract: Embodiments related to semiconductor manufacturing and semiconductor devices with semiconductor structure are described and depicted.Type: ApplicationFiled: March 31, 2015Publication date: July 23, 2015Inventors: Thoralf KAUTZSCH, Boris BINDER, Torsten HELM, Stefan KOLB, Marc PROBST, Uwe RUDOLPH
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Patent number: 8994127Abstract: Embodiments related to semiconductor manufacturing and semiconductor devices with semiconductor structure are described and depicted.Type: GrantFiled: November 24, 2011Date of Patent: March 31, 2015Assignee: Infineon Technologies AGInventors: Thoralf Kautzsch, Boris Binder, Torsten Helm, Stefan Kolb, Marc Probst, Uwe Rudolph
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Patent number: 8889512Abstract: A transistor component and method of forming a transistor component. One embodiment provides a semiconductor arrangement including a semiconductor body having a at least one first trench, a first field electrode arranged in the lower trench section of the at least one first trench and being insulated from the semiconductor body by a field electrode dielectric. A dielectric layer is formed on the first field electrode in the at least one first trench, including depositing a dielectric material on a first side of the semiconductor body and on the field plate at a higher deposition rate than on sidewalls of the at least one first trench.Type: GrantFiled: October 26, 2011Date of Patent: November 18, 2014Assignee: Infineon Technologies Austria AGInventors: Joachim Krumrey, Gerhard Noebauer, Martin Poelzl, Marc Probst
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Publication number: 20130187159Abstract: An integrated circuit includes a first trench disposed in a semiconductor material, wherein a width of the first trench in an upper portion of the first trench adjacent to a surface of the semiconductor material is smaller than a width of the first trench in a lower portion of the first trench, the lower portion being disposed within the semiconductor material, each width being measured in a plane parallel to a surface of the semiconductor material, each width denoting a distance between inner faces of remaining semiconductor material portions or between outer faces of a filling disposed in the first trench, or between an inner face of a remaining semiconductor material portion and an outer face of a filling disposed in the first trench.Type: ApplicationFiled: January 23, 2012Publication date: July 25, 2013Applicant: Infineon Technologies AGInventors: Torsten Helm, Marc Probst, Uwe Rudolph
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Publication number: 20130134530Abstract: Embodiments related to semiconductor manufacturing and semiconductor devices with semiconductor structure are described and depicted.Type: ApplicationFiled: November 24, 2011Publication date: May 30, 2013Inventors: Thoralf KAUTZSCH, Boris BINDER, Torsten HELM, Stefan KOLB, Marc PROBST, Uwe RUDOLPH
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Publication number: 20120040505Abstract: A transistor component and method of forming a transistor component. One embodiment provides a semiconductor arrangement including a semiconductor body having a at least one first trench, a first field electrode arranged in the lower trench section of the at least one first trench and being insulated from the semiconductor body by a field electrode dielectric. A dielectric layer is formed on the first field electrode in the at least one first trench, including depositing a dielectric material on a first side of the semiconductor body and on the field plate at a higher deposition rate than on sidewalls of the at least one first trench.Type: ApplicationFiled: October 26, 2011Publication date: February 16, 2012Applicant: Infineon Technologies Austria AGInventors: Joachim Krumrey, Gerhard Noebauer, Martin Poelzl, Marc Probst
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Patent number: 8072028Abstract: A transistor component and method of forming a transistor component. One embodiment provides a semiconductor arrangement including a semiconductor body having a at least one first trench, a first field electrode arranged in the lower trench section of the at least one first trench and being insulated from the semiconductor body by a field electrode dielectric. A dielectric layer is formed on the first field electrode in the at least one first trench, including depositing a dielectric material on a first side of the semiconductor body and on the field plate at a higher deposition rate than on sidewalls of the at least one first trench.Type: GrantFiled: October 26, 2009Date of Patent: December 6, 2011Assignee: Infineon Technologies Austria AGInventors: Joachim Krumrey, Gerhard Noebauer, Martin Poelzl, Marc Probst
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Publication number: 20110095360Abstract: A transistor component and method of forming a transistor component. One embodiment provides a semiconductor arrangement including a semiconductor body having a at least one first trench, a first field electrode arranged in the lower trench section of the at least one first trench and being insulated from the semiconductor body by a field electrode dielectric. A dielectric layer is formed on the first field electrode in the at least one first trench, including depositing a dielectric material on a first side of the semiconductor body and on the field plate at a higher deposition rate than on sidewalls of the at least one first trench.Type: ApplicationFiled: October 26, 2009Publication date: April 28, 2011Applicant: INFINEON TECHNOLOGIES AUSTRIA AGInventors: Joachim Krumrey, Gerhard Noebauer, Martin Poelzl, Marc Probst