Patents by Inventor Marc Quattromani
Marc Quattromani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20060206635Abstract: A DMA engine, includes, in part, a DMA controller, an associative memory buffer, a request FIFO accepting data transfer requests from a programmable engine, such as a CPU, and a response FIFO that returns the completion status of the transfer requests to the CPU. Each request includes, in part, a target external memory address from which data is to be loaded or to which data is to be stored; a block size, specifying the amount of data to be transferred; and context information. The associative buffer holds data fetched from the external memory; and provides the data to the CPUs for processing. Loading into and storing from the associative buffer is done under the control of the DMA controller. When a request to fetch data from the external memory is processed, the DMA controller allocates a block within the associative buffer and loads the data into the allocated block.Type: ApplicationFiled: March 10, 2006Publication date: September 14, 2006Applicant: PMC-Sierra, Inc.Inventors: Thomas Alexander, Marc Quattromani, Alexander Rekow
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Patent number: 6219773Abstract: A superscalar superpipelined microprocessor having a write buffer located between the core and cache is disclosed. The write buffer is controlled to store the results of write operations to memory until such time as the cache becomes available, such as when no high-priority reads are to be performed. The write buffer includes multiple entries that are split into two circular buffer sections for facilitating the interaction with the two pipelines of the core; cross-dependency tables are provided for each write buffer entry to ensure that the data is written from the write buffer to memory in program order, considering the possibility of prior data present in the opposite section. Non-cacheable reads form memory are also ordered in program order with the writing of data from the write buffer. Features for handling speculative execution, detecting and handling data dependencies and exceptions, and performing special write functions (misaligned writes and gathered writes) are also disclosed.Type: GrantFiled: October 18, 1993Date of Patent: April 17, 2001Assignee: VIA-Cyrix, Inc.Inventors: Raul A. Garibay, Jr., Marc A. Quattromani
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Patent number: 5907860Abstract: A superscalar superpipelined microprocessor having a write buffer located between the core and cache is disclosed. The write buffer is controlled to store the results of write operations to memory until such time as the cache becomes available, such as when no high-priority reads are to be performed. The write buffer includes multiple entries that are split into two circular buffer sections for facilitating the interaction with the two pipelines of the core; cross-dependency tables are provided for each write buffer entry to ensure that the data is written from the write buffer to memory in program order, considering the possibility of prior data present in the opposite section. Non-cacheable reads from memory are also ordered in program order with the writing of data from the write buffer. Features for handling speculative execution, detecting and handling data dependencies and exceptions, and performing special write functions (misaligned writes and gathered writes). are also disclosed.Type: GrantFiled: July 31, 1996Date of Patent: May 25, 1999Assignee: National Semiconductor CorporationInventors: Raul A. Garibay, Jr., Marc A. Quattromani, Mark Bluhm
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Patent number: 5835949Abstract: A system and method of readily identifying and handling self-modifying variable length instructions in a pipelined processor is disclosed employing index tags associated with each stage of the execution pipeline wherein the index tags identify the cache line numbers in the instruction cache from which the instructions originate.Type: GrantFiled: April 2, 1997Date of Patent: November 10, 1998Assignee: National Semiconductor CorporationInventors: Marc A. Quattromani, Raul A. Garibay, Jr., Steven C. McMahan, Mark W. Hervin
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Patent number: 5752274Abstract: An address translation unit is disclosed employing a direct-mapped translation lookaside buffer and a relatively small, associative victim translation lookaside buffer for translating linear addresses to physical addresses expediently and avoiding thrashing, without requiring large amounts of hardware and space.Type: GrantFiled: November 8, 1994Date of Patent: May 12, 1998Assignee: Cyrix CorporationInventors: Raul A. Garibay, Jr., Marc A. Quattromani, Douglas Beard
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Patent number: 5740398Abstract: A superscalar superpipelined microprocessor having a write buffer located between the core and cache is disclosed. The write buffer is controlled to store the results of write operations to memory until such time as the cache becomes available, such as when no high-priority reads are to be performed. The write buffer includes multiple entries that are split into two circular buffer sections for facilitating the interaction with the two pipelines of the core; cross-dependency tables are provided for each write buffer entry to ensure that the data is written from the write buffer to memory in program order, considering the possibility of prior data present in the opposite section. Non-cacheable reads from memory are also ordered in program order with the writing of data from the write buffer. Features for handling speculative execution, detecting and handling data dependencies and exceptions, and performing special write functions (misaligned writes and gathered writes) are also disclosed.Type: GrantFiled: October 18, 1993Date of Patent: April 14, 1998Assignee: Cyrix CorporationInventors: Marc A. Quattromani, Nital Patwa
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Patent number: 5615402Abstract: A superscalar superpipelined microprocessor having a write buffer located between the core and cache is disclosed. The write buffer is controlled to store the results of write operations to memory until such time as the cache becomes available, such as when no high-priority reads are to be performed. The write buffer includes multiple entries that are split into two circular buffer sections for facilitating the interaction with the two pipelines of the core; cross-dependency tables are provided for each write buffer entry to ensure that the data is written from the write buffer to memory in program order, considering the possibility of prior data present in the opposite section. Non-cacheable reads from memory are also ordered in program order with the writing of data from the write buffer. Features for handling speculative execution, detecting and handling data dependencies and exceptions, and performing special write functions (misaligned writes and gathered writes) are also disclosed.Type: GrantFiled: December 14, 1995Date of Patent: March 25, 1997Assignee: Cyrix CorporationInventors: Marc A. Quattromani, Raul A. Garibay, Jr.
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Patent number: 5596740Abstract: A shared interleaved memory having a relatively large number of banks employs circuitry and methodology for resolving bank conflicts without significantly inducing delay into the data path. A first and a second port make data read, data write, and instruction fetch requests to/from the shared interleaved memory by way of asserting a priority signal, an address, and an operand size which are decoded to discern which, if any, memory banks in the interleaved shared memory are needed. In the event of a bank request conflict, the highest priority requester gets all its requested banks and the losing requester gets all nonconflicting requested banks. After the banks in the interleaved memory are allocated, a signal identifying that the losing requester did not receive all its requested banks is generated which does not impact the delay in the data path and accordingly, the losing requester resubmits its request on the next cycle.Type: GrantFiled: January 26, 1995Date of Patent: January 21, 1997Assignee: Cyrix CorporationInventors: Marc A. Quattromani, John K. Eitrheim
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Patent number: 5584009Abstract: A superscalar superpipelined microprocessor having a write buffer located between the core and cache is disclosed. The write buffer is controlled to store the results of write operations to memory until such time as the cache becomes available, such as when no high-priority reads are to be performed. The write buffer includes multiple entries that are split into two circular buffer sections for facilitating the interaction with the two pipelines of the core; cross-dependency tables are provided for each write buffer entry to ensure that the data is written from the write buffer to memory in program order, considering the possibility of prior data present in the opposite section. Non-cacheable reads from memory are also ordered in program order with the writing of data from the write buffer. Features for handling speculative execution, detecting and handling data dependencies and exceptions, and performing special write functions (misaligned writes and gathered writes) are also disclosed.Type: GrantFiled: October 18, 1993Date of Patent: December 10, 1996Assignee: Cyrix CorporationInventors: Raul A. Garibay, Jr., Marc A. Quattromani, Mark Bluhm
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Patent number: 5471598Abstract: A superscalar superpipelined microprocessor having a write buffer located between the core and cache is disclosed. The write buffer is controlled to store the results of write operations to memory until such time as the cache becomes available, such as when no high-priority reads are to performed. The write buffer includes multiple entries that are split into two circular buffer sections for facilitating the interaction with the two pipelines of the core; cross-dependency tables are provided for each write buffer entry to ensure that the data is written from the write buffer to memory in program order, considering the possibility of prior data present in the opposite section. Non-cacheable reads from memory are also ordered in program order with the writing of data from the write buffer. Features for handling speculative execution, detecting and handling data dependencies and exceptions, and performing special write functions (misaligned writes and gathered writes) are also disclosed.Type: GrantFiled: October 18, 1993Date of Patent: November 28, 1995Assignee: Cyrix CorporationInventors: Marc A. Quattromani, Raul A. Garibay, Jr., Nital Patwa, Mark W. Hervin
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Patent number: 5291498Abstract: An error correcting code and apparatus are used in conjunction with a main memory in which a data word is stored in a plurality of circuits each of which produces multiple outputs. A minimum number of check bits are stored together with the data word for detecting and correcting single bit errors and detecting the existence of multi-bit errors. A parity bit for the entire data word is also stored. For a 32-bit data word, at least 3 bits of the data word are stored in each of 10 memory circuits. Seven check bits and one parity bit are also stored in the 10 memory circuits wherein no more than one of the check bits or parity bit is stored in any one memory circuit. Upon reading the data word from the memory a set of verify check bits and a verify parity bit are generated and compared to the stored check bits and stored parity bit to produce a check bit syndrome and a parity bit syndrome.Type: GrantFiled: January 29, 1991Date of Patent: March 1, 1994Assignee: Convex Computer CorporationInventors: James A. Jackson, Marc A. Quattromani, Kevin M. Lowderman