Abstract: A timing circuit for ATE generates an output clock from an input clock and controls output pulse width. The timing circuit includes a differential driver having an input that receives the input clock, and having inverting and non-inverting outputs. The inverting output is coupled to a first phase-locked loop, and the non-inverting output is coupled to a second phase-locked loop. The first and second phase-locked loops respectively generate first and second clocks in response to respective rising and falling edges of the input clock. A combiner circuit converts the first and second clocks into narrow pulse trains, and the pulse trains respectively operate SET and RESET inputs of a SET/RESET flip-flop. The SET/RESET flip-flop generates an output clock having rising edges responsive to rising edges of the input clock, and falling edges responsive to falling edges of the input clock.