Abstract: An (SST) driver circuit having additional circuitry for minimizing data-dependent jitter in the SST driver and increasing frequency amplitude in the SST driver. The additional circuity comprises a plurality of switches configured to be turned on or pulsed on momentarily during operation to discharge a node in the SST output stage for the purpose of removing the stored charge before the next transition cycle of the output stage.

Abstract: A digital frequency multiplier is provided that continues to adjust its multiplied frequency after the desired multiplied frequency is reached, that can be tested during operation and that is easily scalable. The digital frequency multiplier comprises a frequency detector, a frequency adjuster and a ring oscillator (RO). The frequency detector is configured for receiving a reference frequency and an RO output frequency, and for continuously monitoring a difference between the reference frequency and the RO output frequency. Based on the continuously monitored difference, the frequency detector continuously outputs an adjusting signal to the frequency adjuster. In response thereto, the frequency adjuster outputs selection data to the RO that adjusts the oscillation frequency of the RO, and thus the multiplied frequency of the digital frequency multiplier. Testable and growable logic circuitry are provided within the RO that allow the digital frequency multiplier to be tested during operation and easily scaled.