Abstract: A hyperfrequency dynamic divide-by-two frequency divider circuit includes an inverter stage A and a follower stage B, in which the output of the inverter stage is applied to the input of the follower stage via an interrupt transistor T.sub.1 which is controlled by the hyperfrequency input signal H having a frequency f.sub.e. The output Q of the follower stage B is fed back to the input of the inverter stage A and supplies the output signal having a frequency f=f.sub.e /2. The operation of the divider takes place subject to the conditions:1/[(.alpha.+1) Tpd].ltoreq.f.sub.e .ltoreq.1/[(.alpha.+1).tau..sub.1 ]where .alpha.=(T.sub.e -.tau.)/.tau., in which relations .tau..sub.1 is the propagation time in the interrupt transistor, .alpha. is the duty cycle, T.sub.e is the period of the input signal, .tau. is the period during which the interrupt transistor T.sub.

Abstract: A circuit for performing the EXCLUSIVE-OR function of a signal A and a signal B comprises field effect transistors of the MESFET type normally cut off in the absence of a gate-source signal. The circuit also comprises loads and is integrated on a semiconductor substrate of the group III-V. A signal A which is complementary to the signal A is also applied to this circuit. The circuit is formed by a field effect transistor T'.sub.1 whose gate is controlled by the signal B, whose drain receives the signal A via a load R'.sub.1, and whose source receives the signal A which is complementary to the signal A. The signal representing the EXCLUSIVE-OR function (A.sym.B) is available at the junction of the drain of the transistor T'.sub.1 and the load R'.sub.1 and constitutes the output S.sub.1 of the gate.

Abstract: An integrated divide-by-two frequency divider circuit in BFL logic of the master-slave flip-flop type which comprises two complementary outputs Q and Q and only a single input for a control signal. The divider is formed only by NOR gates and wired-OR gates. The master does not have a memory function and the various transistors are proportioned so that, .tau..sub.1 being the transit time in the master, .tau..sub.3 the transit time in the first and the second NOR-gate (G.sub.3 and G.sub.4) of the slave, and .tau..sub.4 the transit time in the fourth and the third NOR gate (G.sub.4 and G.sub.5) of the slave, the following inequality is satisfied .tau..sub.1 =1(.tau..sub.3 +.tau..sub.4), thus resulting in a maximum operating frequency which is defined by the relation f.sub.max =1/(.tau..sub.1 +.tau..sub.3 +.tau..sub.4). This circuit is integrated by means of depletion MESFET transistors on a gallium arsenide substrate in a technology including inverter-type gates which are followed by a level translator stage.