Abstract: In an embodiment a switch includes a first MOS transistor having its source connected to its channel-forming region and coupled with a first terminal of the switch, its drain coupled with a second terminal of the switch, and its gate connected to a first node of the switch, a diode coupling the first terminal with the first node, a capacitive element coupling a third terminal of the switch with the first node, the third terminal being configured to receive a control signal for the switch and a discharge circuit coupling the first node with the first terminal, the discharge circuit configured to conduct only when a voltage between the first node and the first terminal is greater than or equal to a threshold.

Abstract: In an embodiment, a method for soft-starting an SMPS includes: asserting an enable signal; disabling an output stage of the SMPS; after asserting the enable signal, measuring a feedback voltage of the SMPS; receiving a first reference voltage at an input reference node; comparing the measured feedback voltage with the first reference voltage; and, when the measured feedback voltage is lower than the first reference voltage, storing the feedback voltage in a soft-start capacitor, connecting an output reference node to the soft-start capacitor, enabling the output stage of the SMPS, and switching a transistor of the output stage to regulate the output voltage based on the feedback voltage and a second reference voltage at the output reference node, and injecting a current into the soft-start capacitor.

Abstract: A pulse width modulation device includes a switching transistor for defining modulation phases, a capacitor, and switches arranged to: a) in a first phase, charge the capacitor to a voltage corresponding to the on/off threshold of the switching transistor, and b) in a second phase, connect the capacitor between a terminal for applying a setpoint voltage and the gate of the switching transistor. A constant current source is connected to apply a current in the capacitor tending to bring the gate of the switching transistor toward the on/off threshold.

Abstract: A switched capacitor amplifier having an amplification unit adapted to amplify a differential signal; a first switched capacitor block including a first plurality of capacitors operable to sample a first differential input signal during a first sampling phase and to drive the amplification unit during a first drive phase; and a second switched capacitor block including a second plurality of capacitors operable to sample a second differential input signal during a second sampling phase and to drive the amplification unit during a second drive phase.

Abstract: A pulse width modulation device includes a switching transistor for defining modulation phases, a capacitor, and switches arranged to: a) in a first phase, charge the capacitor to a voltage corresponding to the on/off threshold of the switching transistor, and b) in a second phase, connect the capacitor between a terminal for applying a setpoint voltage and the gate of the switching transistor. A constant current source is connected to apply a current in the capacitor tending to bring the gate of the switching transistor toward the on/off threshold.

Abstract: A device may include a programmable gain amplifier and an analog-digital converter with pipeline architecture having several stages. The first stage of the analog-digital converter may incorporate the programmable gain amplifier and an analog-digital conversion circuit with a programmable threshold.

Abstract: The common-mode voltage of a switched-capacitor system is controlled by determining a current common-mode voltage of the switched-capacitor system, converting (in a flow-through conduction cell) the difference between the current common-mode voltage and a desired common-mode voltage into a resultant current, and reinjecting this resultant current into the switched-capacitor system via a resistive path.

Abstract: A voltage regulator includes an amplifier and a regulation loop. The regulator includes a first PMOS transistor connected to a terminal supplying an input voltage, a second PMOS transistor connected in series with the first PMOS transistor. A node between those two transistors defines an output terminal. A first source of a first polarization current of fixed value is connected to the gate of the first transistor, and a second source of a second polarization current of fixed value connects the second transistor to ground. A third NMOS transistor is connected between the two current sources. A circuit is provided to modify automatically at least one of the polarization currents in relation to the load current.

Abstract: A switched capacitor amplifier having an amplification unit adapted to amplify a differential signal; a first switched capacitor block including a first plurality of capacitors operable to sample a first differential input signal during a first sampling phase and to drive the amplification unit during a first drive phase; and a second switched capacitor block including a second plurality of capacitors operable to sample a second differential input signal during a second sampling phase and to drive the amplification unit during a second drive phase.

Abstract: The common-mode voltage of a switched-capacitor system is controlled by determining a current common-mode voltage of the switched-capacitor system, converting (in a flow-through conduction cell) the difference between the current common-mode voltage and a desired common-mode voltage into a resultant current, and reinjecting this resultant current into the switched-capacitor system via a resistive path.

Abstract: The device generates a reference voltage, in particular designed for a system of the switched-capacitor type, based on a setpoint voltage. It includes a regulation loop having a first input to receive the setpoint voltage, and an output stage arranged as a voltage follower and looped to a second input of the loop. An additional stage is configured to deliver the reference voltage to the switched-capacitor system, this additional stage, coupled to the output stage, also being arranged as a voltage follower and paired with the output stage.

Abstract: A device may include a programmable gain amplifier and an analog-digital converter with pipeline architecture having several stages. The first stage of the analog-digital converter may incorporate the programmable gain amplifier and an analog-digital conversion circuit with a programmable threshold.

Abstract: A memory device of SRAM type has a memory plan constituted by base memory cells organized in lines and in columns. Each cell of a column is connected between two bit lines which are precharged during a reading operation. Circuitry is provided for generating a precharge voltage of the bit lines which is less than a nominal supply voltage of the device.

Abstract: A voltage regulator includes an amplifier and a regulation loop. The regulator includes a first PMOS transistor connected to a terminal supplying an input voltage, a second PMOS transistor connected in series with the first PMOS transistor. A node between those two transistors defines an output terminal. A first source of a first polarization current of fixed value is connected to the gate of the first transistor, and a second source of a second polarization current of fixed value connects the second transistor to ground. A third NMOS transistor is connected between the two current sources. A circuit is provided to modify automatically at least one of the polarization currents in relation to the load current.

Abstract: A circuit of generation of a reference voltage by a first MOS transistor connected to a first terminal of application of a supply voltage, the first transistor being in series with a second MOS transistor controlled by an input stage of a transconductance amplifier and their junction point defining an output terminal providing the reference voltage, a first current source connecting the first supply terminal to a gate of the first transistor, a second current source connecting the second transistor to a second terminal of application of the supply voltage, at least one third MOS transistor connecting the two current sources, and a capacitive element directly connecting the output terminal to a conduction terminal of the third transistor to vary the conduction of this third transistor in case of a variation in output voltage.

Abstract: A memory device of SRAM type has a memory plan constituted by base memory cells organized in lines and in columns. Each cell of a column is connected between two bit lines which are precharged during a reading operation. Circuitry is provided for generating a precharge voltage of the bit lines which is less than a nominal supply voltage of the device.

Abstract: A differential amplifier having a first and second output terminals and receiving an input signal at an input terminal. The amplifier comprises a first amplifier having a first input connected to the input terminal, a second input and a first output connected together to the first output terminal, and a second output connected to the second output terminal, the first amplifier reproducing the input signal on the first output. The amplifier comprises a second amplifier having a first input receiving a reference signal and a second input connected to the output terminals by resistive elements and controlling the provision by the first amplifier on the second output of a signal such that the signals received at the first and second inputs of the second amplifier are equal.

Abstract: A circuit of generation of a reference voltage by a first MOS transistor connected to a first terminal of application of a supply voltage, the first transistor being in series with a second MOS transistor controlled by an input stage of a transconductance amplifier and their junction point defining an output terminal providing the reference voltage, a first current source connecting the first supply terminal to a gate of the first transistor, a second current source connecting the second transistor to a second terminal of application of the supply voltage, at least one third MOS transistor connecting the two current sources, and a capacitive element directly connecting the output terminal to a conduction terminal of the third transistor to vary the conduction of this third transistor in case of a variation in output voltage.

Abstract: A circuit for generating a reference current, including, between two terminals of application of a supply voltage: at least a first branch formed of at least a first and of at least a second transistors in series; at least a second branch formed of at least a third and of at least a fourth transistors in series with a switched-capacitance circuit.

Abstract: A circuit of generation of a reference voltage by a first MOS transistor of a first type connected to a first terminal of application of a supply voltage. The first transistor is connected with a second MOS transistor of the same type controlled by an input stage of a transconductance amplifier and their junction point defines an output terminal providing the reference voltage. A first current source of fixed value connects the first supply terminal to the gate of the first transistor, a second current source of fixed value connecting the second transistor to a second terminal of application of the supply voltage.