Abstract: Systems, apparatuses, and methods for error detection and recovery when streaming data are described. A system includes one or more companion direct memory access (DMA) subsystems for transferring data. When an error is detected for a component of the companion DMA subsystem(s), the operations performed by the other components need to gracefully adapt to this error so that operations face only a minimal disruption. For example, while one or more consumers are still consuming a first frame, a companion router receives an indication of an error for a second frame, causing the companion router to send a router frame abort message to a route manager. In response, the route manager waits until the consumer(s) are consuming the second frame before sending them a frame abort message. The consumer(s) flush their pipeline and transition to an idle state waiting for a third frame after receiving the frame abort message.

Abstract: Presented are techniques of identifying, processing and displaying data point clusters associated with map information in an efficient manner Methods and systems are disclosed which process map information to identify clusters of requested data points for display, based on iterative clustering and filtering of the data points. Methods and systems are also disclosed which generate polygons representing the clusters. The amount of data to be processed and/or displayed can be reduced, without loss of any associated information content in a displayed map.

Abstract: Systems, apparatuses, and methods for error detection and recovery when streaming data are described. A system includes one or more companion direct memory access (DMA) subsystems for transferring data. When an error is detected for a component of the companion DMA subsystem(s), the operations performed by the other components need to gracefully adapt to this error so that operations face only a minimal disruption. For example, while one or more consumers are still consuming a first frame, a companion router receives an indication of an error for a second frame, causing the companion router to send a router frame abort message to a route manager. In response, the route manager waits until the consumer(s) are consuming the second frame before sending them a frame abort message. The consumer(s) flush their pipeline and transition to an idle state waiting for a third frame after receiving the frame abort message.

Abstract: Embodiments relate to an image signal processor that includes an image processing circuit, a buffer, and a rate limiter circuit. The image processing circuit perform operations associated with image signal processing. The buffer stores the image data provided by the system memory. The buffer includes a shared that is dynamically allocated among the image processing circuits. The rate limiter circuit arbitrates allocation of the shared section. The arbitration process includes allocating data credits for the shared section to an image processing circuit. The rate limiter circuit determines a first number of blocks in the shared section that are allocated for pending requests and a second number of blocks that include data pending to be consumed by the image processing circuit. If the total allocated blocks occupied by the image processing circuit exceed a throttling threshold, the image processing circuit will be throttled by an exponential factor.

Abstract: Systems, apparatuses, and methods for performing scatter and gather direct memory access (DMA) streaming through a circular buffer are described. A system includes a circular buffer, producer DMA engine, and consumer DMA engine. After the producer DMA engine writes or skips over a given data chunk of a first frame to the buffer, the producer DMA engine sends an updated write pointer to the consumer DMA engine indicating that a data credit has been committed to the buffer and that the data credit is ready to be consumed. After the consumer DMA engine reads or skips over the given data chunk of the first frame from the buffer, the consumer DMA engine sends an updated read pointer to the producer DMA engine indicating that the data credit has been consumed and that space has been freed up in the buffer to be reused by the producer DMA engine.

Abstract: In some embodiments, a system includes a memory system, a real-time computing device, and a controller. The real-time computing device stores data within a local buffer having a corresponding storage threshold, where the data satisfies the storage threshold, and where the storage threshold is based on a latency of the memory system and an expected rate of utilization of the data of the local buffer. The controller detects that the memory system should perform an operation, where the memory system is unavailable to the real-time computing device during the operation. In response to detecting that an amount of time for the operation exceeds an amount of time corresponding to the storage threshold, the controller overrides the storage threshold. The controller may override the storage threshold by modifying the storage threshold and by overriding a default priority for access requests of the real-time computing device to the memory system.

Abstract: Systems, apparatuses, and methods for aggregating memory requests with opportunism in a display pipeline. Memory requests are aggregated for each requestor of a plurality of requestors in the display pipeline. When the number of memory requests for a given requestor reaches a corresponding threshold, memory requests may be issued for the given requestor. In response to determining the given requestor has reached its threshold, other requestors may issue memory requests even if they have not yet aggregated enough memory requests to reach their corresponding thresholds.

Abstract: Presented are techniques of identifying, processing and displaying data point clusters (850, 851) associated with map information (200) in an efficient manner. Methods and systems are disclosed which process map information (200) to identify clusters (850, 851) of requested data points for display (1020), based on iterative clustering and filtering of the data points. Methods and systems are also disclosed which generate polygons (1860, 1861, 1901-05) representing the clusters. The amount of data to be processed and/or displayed can be reduced, without loss of any associated information content in a displayed map.

Abstract: Presented are techniques of identifying, processing and displaying data point clusters (850, 851) associated with map information (200) in an efficient manner. Methods and systems are disclosed which process map information (200) to identify clusters (850, 851) of requested data points for display (1020), based on iterative clustering and filtering of the data points. Methods and systems are also disclosed which generate polygons (1860, 1861, 1901-05) representing the clusters. The amount of data to be processed and/or displayed can be reduced, without loss of any associated information content in a displayed map.

Abstract: In some embodiments, a system includes a memory system, a real-time computing device, and a controller. The real-time computing device stores data within a local buffer having a corresponding storage threshold, where the data satisfies the storage threshold, and where the storage threshold is based on a latency of the memory system and an expected rate of utilization of the data of the local buffer. The controller detects that the memory system should perform an operation, where the memory system is unavailable to the real-time computing device during the operation. In response to detecting that an amount of time for the operation exceeds an amount of time corresponding to the storage threshold, the controller overrides the storage threshold. The controller may override the storage threshold by modifying the storage threshold and by overriding a default priority for access requests of the real-time computing device to the memory system.

Abstract: An apparatus and method of using a cache to improve a learn rate for a content-addressable memory (“CAM”) are disclosed. A network device such as a router or a switch, in one embodiment, includes a key generator, a searching circuit, and a key cache, wherein the key generator is capable of generating a first lookup key in response to a first packet. The searching circuit is configured to search the content of the CAM to match the first lookup key. If the first lookup key is not found in the CAM, the key cache stores the first lookup key in response to a first miss.

Abstract: Methods and apparatus for caching neighbor data in a block processing pipeline that processes blocks in knight's order with quadrow constraints. Stages of the pipeline may maintain two local buffers that contain data from neighbor blocks of a current block. A first buffer contains data from the last C blocks processed at the stage. A second buffer contains data from neighbor blocks on the last row of a previous quadrow. Data for blocks on the bottom row of a quadrow are stored to an external memory at the end of the pipeline. When a block on the top row of a quadrow is input to the pipeline, neighbor data from the bottom row of the previous quadrow is read from the external memory and passed down the pipeline, each stage storing the data in its second buffer and using the neighbor data in the second buffer when processing the block.

Abstract: Block processing pipeline methods and apparatus in which pixel data from a reference frame is prefetched into a search window memory. The search window may include two or more overlapping regions of pixels from the reference frame corresponding to blocks from the rows in the input frame that are currently being processed in the pipeline. Thus, the pipeline may process blocks from multiple rows of an input frame using one set of pixel data from a reference frame that is stored in a shared search window memory. The search window may be advanced by one column of blocks by initiating a prefetch for a next column of reference data from a memory. The pipeline may also include a reference data cache that may be used to cache a portion of a reference frame and from which at least a portion of a prefetch for the search window may be satisfied.

Abstract: Systems, apparatuses, and methods for aggregating memory requests with opportunism in a display pipeline. Memory requests are aggregated for each requestor of a plurality of requestors in the display pipeline. When the number of memory requests for a given requestor reaches a corresponding threshold, memory requests may be issued for the given requestor. In response to determining the given requestor has reached its threshold, other requestors may issue memory requests even if they have not yet aggregated enough memory requests to reach their corresponding thresholds.

Abstract: In an embodiment, a display control unit is configured to transmit read operations to the memory in the system to read image data for processing, and may employ QoS levels with the read operations to ensure that enough data is provided to satisfy the real time display requirements. To determine which QoS level to use for a given read request, the display control unit may be configured to compare an amount of image data in the display control unit (e.g. in various input and/or output buffers in the display control unit) to one or more thresholds. The display control unit may also be configured to dynamically update the thresholds based on a memory stress level in the memory controller.

Abstract: A system in accordance with the invention may include a data memory storing a multi-dimensional (e.g., a two-dimensional) data structure. An address generation unit is provided to calculate real addresses in order to access the multi-dimensional data structure in a desired pattern. The address generation unit may be configured to calculate real addresses by moving across the multi-dimensional data structure between pairs of end points. The pairs of end points (as well as parameters such as the step size between the end points) may be pre-programmed into the address generation unit prior to accessing the multi-dimensional data structure. A processor, such as a vector processor, may be configured to access (e.g., read or write data to) the data structure at the real addresses calculated by the address generation unit.

Abstract: Block processing pipeline methods and apparatus in which pixel data from a reference frame is prefetched into a search window memory. The search window may include two or more overlapping regions of pixels from the reference frame corresponding to blocks from the rows in the input frame that are currently being processed in the pipeline. Thus, the pipeline may process blocks from multiple rows of an input frame using one set of pixel data from a reference frame that is stored in a shared search window memory. The search window may be advanced by one column of blocks by initiating a prefetch for a next column of reference data from a memory. The pipeline may also include a reference data cache that may be used to cache a portion of a reference frame and from which at least a portion of a prefetch for the search window may be satisfied.

Abstract: Methods and apparatus for caching neighbor data in a block processing pipeline that processes blocks in knight's order with quadrow constraints. Stages of the pipeline may maintain two local buffers that contain data from neighbor blocks of a current block. A first buffer contains data from the last C blocks processed at the stage. A second buffer contains data from neighbor blocks on the last row of a previous quadrow. Data for blocks on the bottom row of a quadrow are stored to an external memory at the end of the pipeline. When a block on the top row of a quadrow is input to the pipeline, neighbor data from the bottom row of the previous quadrow is read from the external memory and passed down the pipeline, each stage storing the data in its second buffer and using the neighbor data in the second buffer when processing the block.

Abstract: In an embodiment, a display control unit is configured to transmit read operations to the memory in the system to read image data for processing, and may employ QoS levels with the read operations to ensure that enough data is provided to satisfy the real time display requirements. To determine which QoS level to use for a given read request, the display control unit may be configured to compare an amount of image data in the display control unit (e.g. in various input and/or output buffers in the display control unit) to one or more thresholds. The display control unit may also be configured to dynamically update the thresholds based on a memory stress level in the memory controller.

Abstract: An apparatus, system, and method for providing a multi-dimensional data structure and address generation unit configured to calculate real addresses in order to access the multi-dimensional data structure in a desired pattern. The address generation unit may be configured to calculate the real addresses by executing a series of nested loops pre-programmed into the address generation unit prior to accessing the multi-dimensional data structure. The address generation unit may receive as inputs a set of parameters defining characteristics of the nested loops such as a starting offset, number of iterations or step size for loops, data structure dimensions, or loop starting point inheritance. A vector processor may then access the multi-dimensional data structure at the real addresses calculated by the address generation unit. The multi-dimensional data structure may be stored in a buffer in a data memory.