Abstract: A circuit for measuring current in a power MOS transistor (M0) comprises second (M1) and third (M2) transistors in series of the same type and same technology as, but having a smaller surface than, the power transistor and arranged in parallel on the latter. The two series transistors have their gates connected to the gate of the power transistor. The current in transistor (M2) which is connected to the reference electrode of the power transistor is measured.

Abstract: A dynamic isolation circuit belonging to a monolithic integrated circuit comprising lateral transistors and vertical transistors. The lateral transistors are isolated by an isolating region connected to an isolating potential (V.sub.iso), these lateral transistors being connected up to voltages of a first polarity relative to a reference voltage (GND), the power terminal connected up to the rear face normally being at a potential (V.sub.out) of the first polarity relative to the reference voltage.

Abstract: A current source having a wide range of output voltages. The emitter-collector path of a main transistor (T.sub.30) of the npn type, arranged to define the value of the current, is connected in series with the collector-emitter paths of a plurality of cascaded npn-type output transistors (T.sub.31 . . . T.sub.35). Each output transistor (T.sub.31 . . . T.sub.35) is associated with a respective control transistor (T'.sub.31 . . . T'.sub.35) of the opposite type. At least some of the control transistors have their emitters connected to respective collectors of output transistors of a different rank. This yields an output voltage V.sub.s which can range between small values and a value close to the supply voltage V.sub.c.