Abstract: A method and an apparatus that improves virtual memory management. The proposed method and apparatus provides an application with an efficient channel for communicating information about future behavior of an application with respect to the use of memory and other resources to the OS, a paging daemon, and other system software. The state of hint bits, which are integrated into page table entries and TLB entries and are used for communicating information to the OS, can be changed explicitly with a special instruction or implicitly as a result of referencing the associated page. The latter is useful for canceling hints. The method and apparatus enables memory allocators, garbage collectors, and compilers (such as those used by the Java platform) to use a page-aligned heap and a page-aligned stack to assist the OS in effective management of memory resources. This mechanism can also be used in other system software.

Abstract: A method of providing coherent shared memory access among a plurality of shared memory multiprocessor nodes. For each line of data in each of the nodes, a list of those processors of the node that have copies of the line in their caches is maintained. If a memory command is issued from a processor of one node, and if the command is directed to a line of memory of another node, then the memory command is sent directly to an adapter of the one node. When the adapter receives the command, it forwards the command from the one adapter to another adapter of the other node. When the other adapter receives the command, the command is forwarded to the local memory of the other node. The list of processors is then updated in the local memory of the other node to include or exclude the other adapter depending on the command. If the memory command is issued from one of the processors of one of the nodes, and if the command is directed to a line of memory of the one node, then the command is sent directly to local memory.

Abstract: A memoryless communications adapter for communicating between the nodes of a distributed parallel computer network, each node including a non-shared program memory coupled to the memoryless communications adapter which interfaces the network. An embodiment of the present invention advantageously provides an adapter that can manipulate queues and matching tables efficiently in hardware and provide a high-level object view of queues and matching in the context of communication between nodes. Preferably, the Queue manipulation logic, Match Table manipulation logic and the Sequence Table manipulation logic are implemented in the adapter hardware which does not keep any state or resources in it that depend on the size of the system or the number of queues/tables instantiated. The actual states of these objects may be kept in the program memory, so that the adapter hardware is memoryless.

Abstract: Disclosed is a method and apparatus for improving the performance and connection establishing capability of multi-stage switching networks by providing additional intelligent features in the individual switching apparatus devices at each stage of the network. The invention method is particularly effective in asynchronous circuit-switched networks. The most important feature to be added is adaptivity of the switching apparatus; where adaptivity means the ability of each switching element to determine for itself which of several optional alternate paths to try at each stage of the network based on availability. This is a better approach because it brings the decision directly to the switching apparatus involved, which has the data required to make an intelligent path selection decision to circumvent blocking in the multi-stage network.