Abstract: An encapsulated MEMS device and a method for manufacturing the MEMS device are provided. The method comprises providing a cavity structure having an inner volume comprising a plurality of MEMS elements, which are relatively displaceable with respect to each other, and having an opening structure to the inner volume, depositing a Self-Assembled Monolayer (SAM) through the opening structure onto exposed surfaces within the inner volume of the cavity structure, and closing the cavity structure by applying a layer structure on the opening structure for providing a hermetically closed cavity.

Abstract: A power semiconductor device includes a semiconductor body including a first surface, an edge delimiting the semiconductor body in a horizontal direction substantially parallel to the first surface, an active area including at least one of several transistor structures connected in parallel and several diode structures connected in parallel, and a peripheral area arranged between the active area and the edge. The power semiconductor further device includes a plurality of word lines, a plurality of bit lines separated from the word lines, and a plurality of temperature sensors arranged on or at the first surface, wherein each of the temperature sensors is connected with one of the bit lines and one of the word lines or each of the temperature sensors is formed by a respective portion of one of the bit lines.

Abstract: A power semiconductor device includes a semiconductor body including a first surface, an edge delimiting the semiconductor body in a horizontal direction substantially parallel to the first surface, an active area including at least one of several transistor structures connected in parallel and several diode structures connected in parallel, and a peripheral area arranged between the active area and the edge. The power semiconductor further device includes a plurality of word lines, a plurality of bit lines separated from the word lines, and a plurality of temperature sensors arranged on or at the first surface, wherein each of the temperature sensors is connected with one of the bit lines and one of the word lines or each of the temperature sensors is formed by a respective portion of one of the bit lines.

Abstract: A semiconductor device includes an electrode arranged on a main surface of a semiconductor body and an insulating structure insulating the electrode from the semiconductor body. The insulating structure includes in a vertical cross-section a gate dielectric portion forming a first horizontal interface at least with a drift region of the device and having a first maximum vertical extension between the first horizontal interface and the electrode, and a field dielectric portion forming with the drift region second, third and fourth horizontal interfaces. The second through fourth horizontal interfaces are arranged below the main surface. The third horizontal interface is arranged between the second and fourth horizontal interfaces. A second maximum vertical extension is larger than the first maximum vertical extension and a third maximum vertical extension is larger than the second maximum vertical extension. The electrode only partially overlaps the third horizontal interface.

Abstract: A semiconductor device formed in a semiconductor substrate includes an isolation trench in the semiconductor substrate to laterally insulate adjacent components of the semiconductor device. A lateral isolation layer is disposed in the isolation trench. The semiconductor device further includes a source region and a drain region, and a body region and a drift region disposed between the source region and the drain region. The semiconductor device additionally includes a gate electrode adjacent to at least a portion of the body region and a field plate adjacent to at least a portion of the drift region. A field dielectric layer is disposed between the drift region and the field plate. A top surface of the field dielectric layer is disposed at a greater height measured from a first main surface of the semiconductor substrate than a top surface of the lateral isolation layer.

Abstract: A semiconductor device formed in a semiconductor substrate includes an isolation trench in the semiconductor substrate to laterally insulate adjacent components of the semiconductor device. A lateral isolation layer is disposed in the isolation trench. The semiconductor device further includes a source region and a drain region, and a body region and a drift region disposed between the source region and the drain region. The semiconductor device additionally includes a gate electrode adjacent to at least a portion of the body region and a field plate adjacent to at least a portion of the drift region. A field dielectric layer is disposed between the drift region and the field plate. A top surface of the field dielectric layer is disposed at a greater height measured from a first main surface of the semiconductor substrate than a top surface of the lateral isolation layer.

Abstract: A semiconductor device includes an electrode arranged on a main surface of a semiconductor body and an insulating structure insulating the electrode from the semiconductor body. The insulating structure includes in a vertical cross-section a gate dielectric portion forming a first horizontal interface at least with a drift region of the device and having a first maximum vertical extension between the first horizontal interface and the electrode, and a field dielectric portion forming with the drift region second, third and fourth horizontal interfaces. The second through fourth horizontal interfaces are arranged below the main surface. The third horizontal interface is arranged between the second and fourth horizontal interfaces. A second maximum vertical extension is larger than the first maximum vertical extension and a third maximum vertical extension is larger than the second maximum vertical extension. The electrode only partially overlaps the third horizontal interface.

Abstract: A method produces a semiconductor device including a semiconductor body, an electrode thereon, and an insulating structure insulating the electrode from the semiconductor body. The semiconductor body includes a first contact region of a first conductivity type, a body region of a second conductivity type, a drift region of the first conductivity type, and a second contact region having a higher maximum doping concentration than the drift region. The insulating structure includes a gate dielectric portion forming a first horizontal interface. with the drift region and has a first maximum vertical extension A field dielectric portion forms with the drift region second and third horizontal interfaces arranged below the main surface. A second maximum vertical extension of the field dielectric portion is larger than the first maximum vertical extension. A third maximum vertical extension of the field dielectric portion is larger than the second maximum vertical extension.

Abstract: A method produces a semiconductor device including a semiconductor body, an electrode thereon, and an insulating structure insulating the electrode from the semiconductor body. The semiconductor body includes a first contact region of a first conductivity type, a body region of a second conductivity type, a drift region of the first conductivity type, and a second contact region having a higher maximum doping concentration than the drift region. The insulating structure includes a gate dielectric portion forming a first horizontal interface. with the drift region and has a first maximum vertical extension A field dielectric portion forms with the drift region second and third horizontal interfaces arranged below the main surface. A second maximum vertical extension of the field dielectric portion is larger than the first maximum vertical extension. A third maximum vertical extension of the field dielectric portion is larger than the second maximum vertical extension.

Abstract: A description is given of a concept for reducing shunt currents in a semiconductor body.

Abstract: A method of manufacturing a transistor is disclosed. The method includes forming a first and a second source/drain regions, a channel connecting the first and the second source/drain regions and a gate electrode for controlling the conductivity of the channel. The gate electrode is formed by defining a gate groove in the substrate, and defining a pocket in each of the isolation trenches at a position adjacent to the groove so that the two pockets will be connected with the groove and the groove is disposed between the two pockets. A gate insulating material is provided at an interface between the active area and the groove and at an interface between the active area and the pockets. A gate electrode material is deposited so as to fill the groove and the two pockets.

Abstract: A description is given of a concept for reducing shunt currents in a semiconductor body.

Abstract: In a method for producing a trench transistor, a substrate of a first conduction type is provided and a trench in the substrate and a gate dielectric in the trench are formed. A first conductive filling in the trench as a gate electrode on the gate dielectric and first source and drain regions are formed. An etched-back first conductive filling is produced by etching back the first conductive filling down to a depth below the first source and drain regions and second source and drain regions are formed. The second source and drain regions adjoin the first source and drain regions and extend to a depth at least as far as the etched-back first conductive filling. An insulation spacer above the etched-back first conductive filling is formed in the trench and a second conductive filling is provided in the trench as an upper part of the gate electrode.

Abstract: A method of manufacturing a transistor. In one embodiment, the method includes forming a gate electrode by defining a gate groove in the substrate. A plate-like portion is defined in each of the trenches at a position adjacent to the groove so that the two plate-like portions will be connected with the groove and the groove is disposed between two plate-like portions. In one embodiment, the two plate-like portions are defined by an etching process which selectively etches the isolating material of the isolation trenches with respect to the semiconductor substrate material. A gate insulating material is provided at an interface between the active area and the groove and the interface between the active area and the plate-like portions, and a gate electrode material is deposited so as to fill the groove and the two plate-like portions.

Abstract: In a method for producing a cover for a region of a substrate, first a frame structure is produced in the region of the substrate, and then a cap structure is attached to the frame structure so that the region under the cap structure is covered. Thus, sensitive devices may be protected easily and at low cost from external influences and particularly from a casting material for casting the entire packaged device, which results when a diced chip is cast.

Abstract: A microelectronic device comprises a substrate and a transistor. The transistor comprises a channel region in the substrate, a recess in the channel region, a first dielectric layer and a second dielectric layer. The first dielectric layer comprises a first dielectric material and is deposited at the bottom of the recess. The second dielectric layer comprises a second dielectric material and is deposited at a sidewall of the recess. The dielectric constant of the first dielectric material is higher than the dielectric constant of the second dielectric material. A gate electrode is positioned in the recess and is electrically insulated from the channel region by the first and second dielectric layers.

Abstract: In a method for producing a trench transistor, a substrate of a first conduction type is provided and a trench in the substrate and a gate dielectric in the trench are formed. A first conductive filling in the trench as a gate electrode on the gate dielectric and first source and drain regions are formed. An etched-back first conductive filling is produced by etching back the first conductive filling down to a depth below the first source and drain regions and second source and drain regions are formed. The second source and drain regions adjoin the first source and drain regions and extend to a depth at least as far as the etched-back first conductive filling. An insulation spacer above the etched-back first conductive filling is formed in the trench and a second conductive filling is provided in the trench as an upper part of the gate electrode.

Abstract: A method of manufacturing a transistor is disclosed. The method includes forming a first and a second source/drain regions, a channel connecting the first and the second source/drain regions and a gate electrode for controlling the conductivity of the channel. The gate electrode is formed by defining a gate groove in the substrate, and defining a pocket in each of the isolation trenches at a position adjacent to the groove so that the two pockets will be connected with the groove and the groove is disposed between the two pockets. A gate insulating material is provided at an interface between the active area and the groove and at an interface between the active area and the pockets. A gate electrode material is deposited so as to fill the groove and the two pockets.

Abstract: In a semiconductor memory including an array of memory cells, each memory cell includes a trench capacitor, the trench capacitor including an inner electrode, an outer electrode and a dielectric layer disposed between the inner electrode and the outer electrode, and a selection transistor, the selection transistor including a first source/drain area, a second source/drain area and a channel region disposed between the first source/drain area and the second source/drain area in a recess, the trench capacitor and the selection transistor of each memory cell are disposed side by side, the first source/drain area of the selection transistor being electrically connected to the inner electrode of the trench capacitor, the recess in which the channel region of the selection transistor is formed being located self aligned between the trench capacitor of the memory cell and the trench capacitor of an adjacent memory cell.

Abstract: A memory cell is provided for storing a bit. The memory cell includes a capacitor with capacitor electrodes for storing electric charge and a semiconductor switch with a channel region, the electrical conductivity of which is controllable, for connecting the capacitor to a bit line, via which a bit can be written to and read from the memory cell. The channel region and a metallic terminal region connected to one of the capacitor electrodes form a metal-semiconductor junction.